geemili
/
drm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Possibly fix stanford checker complaints about sarea

main
Keith Whitwell 2003-06-16 10:40:52 +00:00
parent fdf320a1b8
commit 9e7d6177d1
2 changed files with 30 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
shared-core/radeon_state.c
View File

@ -888,15 +888,14 @@ typedef struct {
static void radeon_cp_dispatch_vertex( drm_device_t *dev, static void radeon_cp_dispatch_vertex( drm_device_t *dev,
drm_buf_t *buf, drm_buf_t *buf,
drm_radeon_tcl_prim_t *prim, drm_radeon_tcl_prim_t *prim )
drm_clip_rect_t *boxes,
int nbox )
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
drm_clip_rect_t box; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start; int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
int numverts = (int)prim->numverts; int numverts = (int)prim->numverts;
int nbox = sarea_priv->nbox;
int i = 0; int i = 0;
RING_LOCALS; RING_LOCALS;
@ -916,10 +915,8 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
do { do {
/* Emit the next cliprect */ /* Emit the next cliprect */
if ( i < nbox ) { if ( i < nbox ) {
if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) radeon_emit_clip_rect( dev_priv,
return; &sarea_priv->boxes[i] );
radeon_emit_clip_rect( dev_priv, &box );
} }
/* Emit the vertex buffer rendering commands */ /* Emit the vertex buffer rendering commands */
@ -998,18 +995,17 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
static void radeon_cp_dispatch_indices( drm_device_t *dev, static void radeon_cp_dispatch_indices( drm_device_t *dev,
drm_buf_t *elt_buf, drm_buf_t *elt_buf,
drm_radeon_tcl_prim_t *prim, drm_radeon_tcl_prim_t *prim )
drm_clip_rect_t *boxes,
int nbox )
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
drm_clip_rect_t box; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + prim->offset; int offset = dev_priv->agp_buffers_offset + prim->offset;
u32 *data; u32 *data;
int dwords; int dwords;
int i = 0; int i = 0;
int start = prim->start + RADEON_INDEX_PRIM_OFFSET; int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
int count = (prim->finish - start) / sizeof(u16); int count = (prim->finish - start) / sizeof(u16);
int nbox = sarea_priv->nbox;
DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
prim->prim, prim->prim,
@ -1048,12 +1044,9 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
(count << RADEON_NUM_VERTICES_SHIFT) ); (count << RADEON_NUM_VERTICES_SHIFT) );
do { do {
if ( i < nbox ) { if ( i < nbox )
if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) radeon_emit_clip_rect( dev_priv,
return; &sarea_priv->boxes[i] );
radeon_emit_clip_rect( dev_priv, &box );
}
radeon_cp_dispatch_indirect( dev, elt_buf, radeon_cp_dispatch_indirect( dev, elt_buf,
prim->start, prim->start,
@ -1453,9 +1446,7 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS )
prim.numverts = vertex.count; prim.numverts = vertex.count;
prim.vc_format = dev_priv->sarea_priv->vc_format; prim.vc_format = dev_priv->sarea_priv->vc_format;
radeon_cp_dispatch_vertex( dev, buf, &prim, radeon_cp_dispatch_vertex( dev, buf, &prim );
dev_priv->sarea_priv->boxes,
dev_priv->sarea_priv->nbox );
} }
if (vertex.discard) { if (vertex.discard) {
@ -1553,9 +1544,7 @@ int radeon_cp_indices( DRM_IOCTL_ARGS )
prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
prim.vc_format = dev_priv->sarea_priv->vc_format; prim.vc_format = dev_priv->sarea_priv->vc_format;
radeon_cp_dispatch_indices( dev, buf, &prim, radeon_cp_dispatch_indices( dev, buf, &prim );
dev_priv->sarea_priv->boxes,
dev_priv->sarea_priv->nbox );
if (elts.discard) { if (elts.discard) {
radeon_cp_discard_buffer( dev, buf ); radeon_cp_discard_buffer( dev, buf );
} }
@ -1772,16 +1761,12 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS )
tclprim.offset = prim.numverts * 64; tclprim.offset = prim.numverts * 64;
tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
radeon_cp_dispatch_indices( dev, buf, &tclprim, radeon_cp_dispatch_indices( dev, buf, &tclprim );
sarea_priv->boxes,
sarea_priv->nbox);
} else { } else {
tclprim.numverts = prim.numverts; tclprim.numverts = prim.numverts;
tclprim.offset = 0; /* not used */ tclprim.offset = 0; /* not used */
radeon_cp_dispatch_vertex( dev, buf, &tclprim, radeon_cp_dispatch_vertex( dev, buf, &tclprim );
sarea_priv->boxes,
sarea_priv->nbox);
} }
if (sarea_priv->nbox == 1) if (sarea_priv->nbox == 1)

45
shared/radeon_state.c
View File

@ -888,15 +888,14 @@ typedef struct {
static void radeon_cp_dispatch_vertex( drm_device_t *dev, static void radeon_cp_dispatch_vertex( drm_device_t *dev,
drm_buf_t *buf, drm_buf_t *buf,
drm_radeon_tcl_prim_t *prim, drm_radeon_tcl_prim_t *prim )
drm_clip_rect_t *boxes,
int nbox )
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
drm_clip_rect_t box; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start; int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
int numverts = (int)prim->numverts; int numverts = (int)prim->numverts;
int nbox = sarea_priv->nbox;
int i = 0; int i = 0;
RING_LOCALS; RING_LOCALS;
@ -916,10 +915,8 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
do { do {
/* Emit the next cliprect */ /* Emit the next cliprect */
if ( i < nbox ) { if ( i < nbox ) {
if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) radeon_emit_clip_rect( dev_priv,
return; &sarea_priv->boxes[i] );
radeon_emit_clip_rect( dev_priv, &box );
} }
/* Emit the vertex buffer rendering commands */ /* Emit the vertex buffer rendering commands */
@ -998,18 +995,17 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
static void radeon_cp_dispatch_indices( drm_device_t *dev, static void radeon_cp_dispatch_indices( drm_device_t *dev,
drm_buf_t *elt_buf, drm_buf_t *elt_buf,
drm_radeon_tcl_prim_t *prim, drm_radeon_tcl_prim_t *prim )
drm_clip_rect_t *boxes,
int nbox )
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
drm_clip_rect_t box; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + prim->offset; int offset = dev_priv->agp_buffers_offset + prim->offset;
u32 *data; u32 *data;
int dwords; int dwords;
int i = 0; int i = 0;
int start = prim->start + RADEON_INDEX_PRIM_OFFSET; int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
int count = (prim->finish - start) / sizeof(u16); int count = (prim->finish - start) / sizeof(u16);
int nbox = sarea_priv->nbox;
DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
prim->prim, prim->prim,
@ -1048,12 +1044,9 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
(count << RADEON_NUM_VERTICES_SHIFT) ); (count << RADEON_NUM_VERTICES_SHIFT) );
do { do {
if ( i < nbox ) { if ( i < nbox )
if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) )) radeon_emit_clip_rect( dev_priv,
return; &sarea_priv->boxes[i] );
radeon_emit_clip_rect( dev_priv, &box );
}
radeon_cp_dispatch_indirect( dev, elt_buf, radeon_cp_dispatch_indirect( dev, elt_buf,
prim->start, prim->start,
@ -1453,9 +1446,7 @@ int radeon_cp_vertex( DRM_IOCTL_ARGS )
prim.numverts = vertex.count; prim.numverts = vertex.count;
prim.vc_format = dev_priv->sarea_priv->vc_format; prim.vc_format = dev_priv->sarea_priv->vc_format;
radeon_cp_dispatch_vertex( dev, buf, &prim, radeon_cp_dispatch_vertex( dev, buf, &prim );
dev_priv->sarea_priv->boxes,
dev_priv->sarea_priv->nbox );
} }
if (vertex.discard) { if (vertex.discard) {
@ -1553,9 +1544,7 @@ int radeon_cp_indices( DRM_IOCTL_ARGS )
prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
prim.vc_format = dev_priv->sarea_priv->vc_format; prim.vc_format = dev_priv->sarea_priv->vc_format;
radeon_cp_dispatch_indices( dev, buf, &prim, radeon_cp_dispatch_indices( dev, buf, &prim );
dev_priv->sarea_priv->boxes,
dev_priv->sarea_priv->nbox );
if (elts.discard) { if (elts.discard) {
radeon_cp_discard_buffer( dev, buf ); radeon_cp_discard_buffer( dev, buf );
} }
@ -1772,16 +1761,12 @@ int radeon_cp_vertex2( DRM_IOCTL_ARGS )
tclprim.offset = prim.numverts * 64; tclprim.offset = prim.numverts * 64;
tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
radeon_cp_dispatch_indices( dev, buf, &tclprim, radeon_cp_dispatch_indices( dev, buf, &tclprim );
sarea_priv->boxes,
sarea_priv->nbox);
} else { } else {
tclprim.numverts = prim.numverts; tclprim.numverts = prim.numverts;
tclprim.offset = 0; /* not used */ tclprim.offset = 0; /* not used */
radeon_cp_dispatch_vertex( dev, buf, &tclprim, radeon_cp_dispatch_vertex( dev, buf, &tclprim );
sarea_priv->boxes,
sarea_priv->nbox);
} }
if (sarea_priv->nbox == 1) if (sarea_priv->nbox == 1)