fix some issues with radeon interrupt handling
From: Dave Airlie + Benjamin Herrenschmidtmain
parent
246c617c87
commit
9f2f010763
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@ -35,6 +35,14 @@
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#include "radeon_drm.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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#include "radeon_drv.h"
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static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 mask)
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{
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u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
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if (irqs)
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RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
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return irqs;
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}
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/* Interrupts - Used for device synchronization and flushing in the
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/* Interrupts - Used for device synchronization and flushing in the
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* following circumstances:
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* following circumstances:
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*
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*
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@ -63,8 +71,8 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
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/* Only consider the bits we're interested in - others could be used
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/* Only consider the bits we're interested in - others could be used
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* outside the DRM
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* outside the DRM
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*/
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*/
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stat = RADEON_READ(RADEON_GEN_INT_STATUS)
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stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
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& (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
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RADEON_CRTC_VBLANK_STAT));
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if (!stat)
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if (!stat)
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return IRQ_NONE;
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return IRQ_NONE;
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@ -80,19 +88,9 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
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drm_vbl_send_signals(dev);
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drm_vbl_send_signals(dev);
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}
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}
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/* Acknowledge interrupts we handle */
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RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv)
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{
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u32 tmp = RADEON_READ(RADEON_GEN_INT_STATUS)
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& (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
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if (tmp)
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RADEON_WRITE(RADEON_GEN_INT_STATUS, tmp);
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}
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static int radeon_emit_irq(drm_device_t * dev)
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static int radeon_emit_irq(drm_device_t * dev)
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{
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_private_t *dev_priv = dev->dev_private;
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@ -122,11 +120,6 @@ static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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/* This is a hack to work around mysterious freezes on certain
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* systems:
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*/
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radeon_acknowledge_irqs(dev_priv);
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DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
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DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
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RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
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RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
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@ -145,7 +138,7 @@ int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence)
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return DRM_ERR(EINVAL);
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return DRM_ERR(EINVAL);
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}
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}
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radeon_acknowledge_irqs(dev_priv);
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radeon_acknowledge_irqs(dev_priv, RADEON_CRTC_VBLANK_STAT);
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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@ -221,7 +214,8 @@ void radeon_driver_irq_preinstall(drm_device_t * dev)
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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/* Clear bits if they're already high */
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/* Clear bits if they're already high */
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radeon_acknowledge_irqs(dev_priv);
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radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
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RADEON_CRTC_VBLANK_STAT));
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}
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}
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void radeon_driver_irq_postinstall(drm_device_t * dev)
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void radeon_driver_irq_postinstall(drm_device_t * dev)
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