Add some new via chipsets.

Disable 3D functionality and AGP DMA for chipsets with the DX9 3D engine.

shared-core/drm_pciids.txt

@@ -219,7 +219,9 @@
 0x1106 0x3122 0 "VIA CLE266"
 0x1106 0x7205 0 "VIA KM400"
 0x1106 0x3108 0 "VIA K8M800"
-0x1106 0x3344 0 "VIA P4VM800PRO"
+0x1106 0x3344 0 "VIA CN700 / VM800 / P4M800Pro"
+0x1106 0x3343 0 "VIA P4M890"
+0x1106 0x3230 VIA_DX9_0 "VIA K8M890"
 
 [i810]
 0x8086 0x7121 0 "Intel i810 GMCH"

shared-core/via_drv.h

@@ -83,7 +83,7 @@ typedef struct drm_via_private {
 	char pci_buf[VIA_PCI_BUF_SIZE];
 	const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE];
 	uint32_t num_fire_offsets;
-	int pro_group_a;
+	int chipset;
 	drm_via_irq_t via_irqs[VIA_NUM_IRQS];
 	unsigned num_irqs;
 	maskarray_t *irq_masks;
@@ -105,8 +105,9 @@ typedef struct drm_via_private {
 } drm_via_private_t;
 
 enum via_family {
-	VIA_OTHER = 0,
+  VIA_OTHER = 0,     /* Baseline */
-	VIA_PRO_GROUP_A,
+  VIA_PRO_GROUP_A,   /* Another video engine and DMA commands */
+  VIA_DX9_0          /* Same video as pro_group_a, but 3D is unsupported */
 };
 
 /* VIA MMIO register access */

shared-core/via_irq.c

@@ -267,12 +267,16 @@ void via_driver_irq_preinstall(drm_device_t * dev)
 		dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
 		dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING;
 
-		dev_priv->irq_masks = (dev_priv->pro_group_a) ?
+		if (dev_priv->chipset == VIA_PRO_GROUP_A ||
-			via_pro_group_a_irqs : via_unichrome_irqs;
+		    dev_priv->chipset == VIA_DX9_0) {
-		dev_priv->num_irqs = (dev_priv->pro_group_a) ?
+			dev_priv->irq_masks = via_pro_group_a_irqs;
-			via_num_pro_group_a : via_num_unichrome;
+			dev_priv->num_irqs = via_num_pro_group_a;
-		dev_priv->irq_map = (dev_priv->pro_group_a) ?
+			dev_priv->irq_map = via_irqmap_pro_group_a;
-			via_irqmap_pro_group_a : via_irqmap_unichrome;
+		} else {
+			dev_priv->irq_masks = via_unichrome_irqs;
+			dev_priv->num_irqs = via_num_unichrome;
+			dev_priv->irq_map = via_irqmap_unichrome;
+		}
 
 		for(i=0; i < dev_priv->num_irqs; ++i) {
 			atomic_set(&cur_irq->irq_received, 0);

shared-core/via_map.c

@@ -107,8 +107,7 @@ int via_driver_load(drm_device_t *dev, unsigned long chipset)
 
 	dev->dev_private = (void *)dev_priv;
 
-	if (chipset == VIA_PRO_GROUP_A)
+	dev_priv->chipset = chipset;
-		dev_priv->pro_group_a = 1;
 
 #ifdef VIA_HAVE_CORE_MM
 	ret = drm_sman_init(&dev_priv->sman, 2, 12, 8);

shared-core/via_verifier.c

@@ -978,7 +978,13 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size,
 	uint32_t cmd;
 	const uint32_t *buf_end = buf + (size >> 2);
 	verifier_state_t state = state_command;
-	int pro_group_a = dev_priv->pro_group_a;
+	int cme_video;
+	int supported_3d;
+
+	cme_video = (dev_priv->chipset == VIA_PRO_GROUP_A ||
+		     dev_priv->chipset == VIA_DX9_0);
+
+	supported_3d = dev_priv->chipset != VIA_DX9_0;
 
 	hc_state->dev = dev;
 	hc_state->unfinished = no_sequence;
@@ -1003,17 +1009,21 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size,
 			state = via_check_vheader6(&buf, buf_end);
 			break;
 		case state_command:
-			if (HALCYON_HEADER2 == (cmd = *buf))
+			if ((HALCYON_HEADER2 == (cmd = *buf)) && 
+			    supported_3d)
 				state = state_header2;
 			else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
 				state = state_header1;
-			else if (pro_group_a
+			else if (cme_video
 				 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5)
 				state = state_vheader5;
-			else if (pro_group_a
+			else if (cme_video
 				 && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
 				state = state_vheader6;
-			else {
+			else if ((cmd == HALCYON_HEADER2) && !supported_3d) {
+				DRM_ERROR("Accelerated 3D is not supported on this chipset yet.\n");
+				state = state_error;
+			} else {
 				DRM_ERROR
 				    ("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
 				     cmd);