intel: Merge latest i915_drm.h
This was not done as a straight copy because reset_stats IOCTL landed in libdrm before upstream kernel. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>main
Ben Widawsky
parent
3d34fe2495
commit
a254cb5041
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@ -27,12 +27,36 @@
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#ifndef _I915_DRM_H_
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#define _I915_DRM_H_
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#include "drm.h"
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#include <drm.h>
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints.
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*/
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/**
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* DOC: uevents generated by i915 on it's device node
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*
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* I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
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* event from the gpu l3 cache. Additional information supplied is ROW,
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* BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
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* track of these events and if a specific cache-line seems to have a
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* persistent error remap it with the l3 remapping tool supplied in
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* intel-gpu-tools. The value supplied with the event is always 1.
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*
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* I915_ERROR_UEVENT - Generated upon error detection, currently only via
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* hangcheck. The error detection event is a good indicator of when things
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* began to go badly. The value supplied with the event is a 1 upon error
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* detection, and a 0 upon reset completion, signifying no more error
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* exists. NOTE: Disabling hangcheck or reset via module parameter will
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* cause the related events to not be seen.
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*
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* I915_RESET_UEVENT - Event is generated just before an attempt to reset the
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* the GPU. The value supplied with the event is always 1. NOTE: Disable
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* reset via module parameter will cause this event to not be seen.
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*/
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#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
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#define I915_ERROR_UEVENT "ERROR"
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#define I915_RESET_UEVENT "RESET"
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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*/
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@ -195,8 +219,8 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_GEM_WAIT 0x2c
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#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
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#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
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#define DRM_I915_GEM_SET_CACHEING 0x2f
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#define DRM_I915_GEM_GET_CACHEING 0x30
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#define DRM_I915_GEM_SET_CACHING 0x2f
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#define DRM_I915_GEM_GET_CACHING 0x30
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#define DRM_I915_REG_READ 0x31
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#define DRM_I915_GET_RESET_STATS 0x32
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@ -223,8 +247,8 @@ typedef struct _drm_i915_sarea {
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#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
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#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
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#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
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#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing)
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#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing)
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#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
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#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
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#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
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#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
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#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
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@ -305,7 +329,14 @@ typedef struct drm_i915_irq_wait {
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#define I915_PARAM_HAS_LLC 17
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#define I915_PARAM_HAS_ALIASING_PPGTT 18
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#define I915_PARAM_HAS_WAIT_TIMEOUT 19
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#define I915_PARAM_HAS_VEBOX 22
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#define I915_PARAM_HAS_SEMAPHORES 20
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#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
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#define I915_PARAM_HAS_VEBOX 22
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#define I915_PARAM_HAS_SECURE_BATCHES 23
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#define I915_PARAM_HAS_PINNED_BATCHES 24
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#define I915_PARAM_HAS_EXEC_NO_RELOC 25
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#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
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#define I915_PARAM_HAS_WT 27
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typedef struct drm_i915_getparam {
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int param;
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@ -626,7 +657,11 @@ struct drm_i915_gem_exec_object2 {
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__u64 offset;
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#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
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#define EXEC_OBJECT_NEEDS_GTT (1<<1)
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#define EXEC_OBJECT_WRITE (1<<2)
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#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
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__u64 flags;
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__u64 rsvd1;
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__u64 rsvd2;
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};
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@ -672,6 +707,34 @@ struct drm_i915_gem_execbuffer2 {
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/** Resets the SO write offset registers for transform feedback on gen7. */
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#define I915_EXEC_GEN7_SOL_RESET (1<<8)
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/** Request a privileged ("secure") batch buffer. Note only available for
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* DRM_ROOT_ONLY | DRM_MASTER processes.
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*/
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#define I915_EXEC_SECURE (1<<9)
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/** Inform the kernel that the batch is and will always be pinned. This
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* negates the requirement for a workaround to be performed to avoid
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* an incoherent CS (such as can be found on 830/845). If this flag is
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* not passed, the kernel will endeavour to make sure the batch is
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* coherent with the CS before execution. If this flag is passed,
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* userspace assumes the responsibility for ensuring the same.
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*/
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#define I915_EXEC_IS_PINNED (1<<10)
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/** Provide a hint to the kernel that the command stream and auxilliary
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* state buffers already holds the correct presumed addresses and so the
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* relocation process may be skipped if no buffers need to be moved in
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* preparation for the execbuffer.
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*/
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#define I915_EXEC_NO_RELOC (1<<11)
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/** Use the reloc.handle as an index into the exec object array rather
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* than as the per-file handle.
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*/
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#define I915_EXEC_HANDLE_LUT (1<<12)
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#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
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#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
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#define i915_execbuffer2_set_context_id(eb2, context) \
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(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
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@ -708,21 +771,45 @@ struct drm_i915_gem_busy {
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__u32 busy;
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};
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#define I915_CACHEING_NONE 0
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#define I915_CACHEING_CACHED 1
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/**
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* I915_CACHING_NONE
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*
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* GPU access is not coherent with cpu caches. Default for machines without an
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* LLC.
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*/
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#define I915_CACHING_NONE 0
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/**
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* I915_CACHING_CACHED
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*
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* GPU access is coherent with cpu caches and furthermore the data is cached in
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* last-level caches shared between cpu cores and the gpu GT. Default on
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* machines with HAS_LLC.
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*/
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#define I915_CACHING_CACHED 1
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/**
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* I915_CACHING_DISPLAY
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*
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* Special GPU caching mode which is coherent with the scanout engines.
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* Transparently falls back to I915_CACHING_NONE on platforms where no special
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* cache mode (like write-through or gfdt flushing) is available. The kernel
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* automatically sets this mode when using a buffer as a scanout target.
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* Userspace can manually set this mode to avoid a costly stall and clflush in
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* the hotpath of drawing the first frame.
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*/
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#define I915_CACHING_DISPLAY 2
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struct drm_i915_gem_cacheing {
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struct drm_i915_gem_caching {
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/**
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* Handle of the buffer to set/get the cacheing level of. */
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* Handle of the buffer to set/get the caching level of. */
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__u32 handle;
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/**
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* Cacheing level to apply or return value
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*
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* bits0-15 are for generic cacheing control (i.e. the above defined
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* bits0-15 are for generic caching control (i.e. the above defined
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* values). bits16-31 are reserved for platform-specific variations
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* (e.g. l3$ caching on gen7). */
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__u32 cacheing;
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__u32 caching;
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};
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#define I915_TILING_NONE 0
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@ -962,4 +1049,4 @@ struct drm_i915_reset_stats {
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__u32 pad;
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};
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#endif /* _I915_DRM_H_ */
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#endif /* _I915_DRM_H_ */
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