nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition
- fix offset for nv04 - use it in nv10 graph ctx switch for getting next channel - dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+main
parent
4182fce408
commit
a331d2e352
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@ -227,8 +227,10 @@ nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int channel;
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if (dev_priv->card_type < NV_40) {
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channel = (NV_READ(0x400704) >> 20) & 0x1f;
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if (dev_priv->card_type < NV_10) {
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channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
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} else if (dev_priv->card_type < NV_40) {
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channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
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} else
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if (dev_priv->card_type < NV_50) {
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uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 4;
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@ -283,16 +285,22 @@ nouveau_graph_dump_trap_info(struct drm_device *dev)
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t address;
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uint32_t channel, class;
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uint32_t method, subc, data;
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uint32_t method, subc, data, data2;
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uint32_t nsource, nstatus;
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if (nouveau_graph_trapped_channel(dev, &channel))
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channel = -1;
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address = NV_READ(0x400704);
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subc = (address >> 16) & 0x7;
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data = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
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address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);
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method = address & 0x1FFC;
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data = NV_READ(0x400708);
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if (dev_priv->card_type < NV_10) {
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subc = (address >> 13) & 0x7;
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data2= 0;
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} else {
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subc = (address >> 16) & 0x7;
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data2= NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
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}
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nsource = NV_READ(NV03_PGRAPH_NSOURCE);
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nstatus = NV_READ(NV03_PGRAPH_NSTATUS);
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if (dev_priv->card_type < NV_50) {
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@ -309,8 +317,8 @@ nouveau_graph_dump_trap_info(struct drm_device *dev)
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ARRAY_SIZE(nouveau_nstatus_names));
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printk("\n");
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DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x\n",
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channel, subc, class, method, data);
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DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x:0x%08x\n",
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channel, subc, class, method, data2, data);
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}
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static void nouveau_pgraph_irq_handler(struct drm_device *dev)
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@ -15,9 +15,6 @@
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# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
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# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
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#define NV03_PGRAPH_STATUS 0x004006b0
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#define NV04_PGRAPH_STATUS 0x00400700
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#define NV_RAMIN 0x00700000
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#define NV_RAMHT_HANDLE_OFFSET 0
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@ -264,7 +261,12 @@
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#define NV04_PGRAPH_BLIMIT5 0x00400698
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#define NV04_PGRAPH_BSWIZZLE2 0x0040069C
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#define NV04_PGRAPH_BSWIZZLE5 0x004006A0
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#define NV03_PGRAPH_STATUS 0x004006B0
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#define NV04_PGRAPH_STATUS 0x00400700
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#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704
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#define NV04_PGRAPH_TRAPPED_DATA 0x00400708
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#define NV04_PGRAPH_SURFACE 0x0040070C
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#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C
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#define NV04_PGRAPH_STATE 0x00400710
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#define NV10_PGRAPH_SURFACE 0x00400710
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#define NV04_PGRAPH_NOTIFY 0x00400714
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@ -594,7 +594,7 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
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return;
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}
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chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
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chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20)&(nouveau_fifo_number(dev)-1);
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next = dev_priv->fifos[chid];
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if (!next) {
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