nouveau: nv20 graph_create_context difference
nv20 writes the chan->id to a different place than nv28. This still does not make nv20 run nv10_demo.main
parent
afc57ef1df
commit
a72eb27fbc
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@ -3004,12 +3004,14 @@ int nv20_graph_create_context(struct nouveau_channel *chan)
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
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void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
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unsigned int ctx_size;
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unsigned int ctx_size;
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unsigned int idoffs = 0x28/4;
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int ret;
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int ret;
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switch (dev_priv->chipset) {
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switch (dev_priv->chipset) {
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case 0x20:
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case 0x20:
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ctx_size = NV20_GRCTX_SIZE;
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ctx_size = NV20_GRCTX_SIZE;
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ctx_init = nv20_graph_context_init;
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ctx_init = nv20_graph_context_init;
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idoffs = 0;
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break;
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break;
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case 0x25:
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case 0x25:
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case 0x28:
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case 0x28:
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@ -3048,7 +3050,7 @@ int nv20_graph_create_context(struct nouveau_channel *chan)
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ctx_init(dev, chan->ramin_grctx->gpuobj);
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ctx_init(dev, chan->ramin_grctx->gpuobj);
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/* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
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/* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
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INSTANCE_WR(chan->ramin_grctx->gpuobj, 0x28/4, (chan->id<<24)|0x1);
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INSTANCE_WR(chan->ramin_grctx->gpuobj, idoffs, (chan->id<<24)|0x1);
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/* CTX_USER */
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/* CTX_USER */
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INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
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INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
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