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add R200_EMIT_RB3D_BLENDCOLOR state packet to support GL_EXT_blend_color, 

GL_EXT_blend_func_separate and GL_EXT_blend_equation_separate on r200
main
Roland Scheidegger 2004-05-18 23:03:22 +00:00
parent 8350382cb1
commit aa142ff1b5
7 changed files with 15 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
shared-core/radeon_drm.h
View File

@ -144,7 +144,8 @@
#define RADEON_EMIT_PP_TEX_SIZE_0 73 #define RADEON_EMIT_PP_TEX_SIZE_0 73
#define RADEON_EMIT_PP_TEX_SIZE_1 74 #define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75 #define RADEON_EMIT_PP_TEX_SIZE_2 75
#define RADEON_MAX_STATE_PACKETS 76 #define R200_EMIT_RB3D_BLENDCOLOR 76
#define RADEON_MAX_STATE_PACKETS 77
/* Commands understood by cmd_buffer ioctl. More can be added but /* Commands understood by cmd_buffer ioctl. More can be added but

1
shared-core/radeon_drv.h
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@ -690,6 +690,7 @@ extern void radeon_do_release(drm_device_t *dev);
#define R200_SE_VTX_FMT_1 0x208c #define R200_SE_VTX_FMT_1 0x208c
#define R200_RE_CNTL 0x1c50 #define R200_RE_CNTL 0x1c50
#define R200_RB3D_BLENDCOLOR 0x3218
/* Constants */ /* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */

4
shared-core/radeon_state.c
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@ -201,6 +201,7 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
case RADEON_EMIT_PP_TEX_SIZE_0: case RADEON_EMIT_PP_TEX_SIZE_0:
case RADEON_EMIT_PP_TEX_SIZE_1: case RADEON_EMIT_PP_TEX_SIZE_1:
case RADEON_EMIT_PP_TEX_SIZE_2: case RADEON_EMIT_PP_TEX_SIZE_2:
case R200_EMIT_RB3D_BLENDCOLOR:
/* These packets don't contain memory offsets */ /* These packets don't contain memory offsets */
break; break;
@ -562,7 +563,8 @@ static struct {
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" }, { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
{ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
}; };

4
shared/radeon.h
View File

@ -51,7 +51,7 @@
#define DRIVER_DATE "20020828" #define DRIVER_DATE "20020828"
#define DRIVER_MAJOR 1 #define DRIVER_MAJOR 1
#define DRIVER_MINOR 10 #define DRIVER_MINOR 11
#define DRIVER_PATCHLEVEL 0 #define DRIVER_PATCHLEVEL 0
/* Interface history: /* Interface history:
@ -84,6 +84,8 @@
* 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
* clients use to tell the DRM where they think the framebuffer is * clients use to tell the DRM where they think the framebuffer is
* located in the card's address space * located in the card's address space
* 1.11 Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
* and GL_EXT_blend_[func|equation]_separate on r200
*/ */
#define DRIVER_IOCTLS \ #define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \ [DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \

3
shared/radeon_drm.h
View File

@ -144,7 +144,8 @@
#define RADEON_EMIT_PP_TEX_SIZE_0 73 #define RADEON_EMIT_PP_TEX_SIZE_0 73
#define RADEON_EMIT_PP_TEX_SIZE_1 74 #define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75 #define RADEON_EMIT_PP_TEX_SIZE_2 75
#define RADEON_MAX_STATE_PACKETS 76 #define R200_EMIT_RB3D_BLENDCOLOR 76
#define RADEON_MAX_STATE_PACKETS 77
/* Commands understood by cmd_buffer ioctl. More can be added but /* Commands understood by cmd_buffer ioctl. More can be added but

1
shared/radeon_drv.h
View File

@ -690,6 +690,7 @@ extern void radeon_do_release(drm_device_t *dev);
#define R200_SE_VTX_FMT_1 0x208c #define R200_SE_VTX_FMT_1 0x208c
#define R200_RE_CNTL 0x1c50 #define R200_RE_CNTL 0x1c50
#define R200_RB3D_BLENDCOLOR 0x3218
/* Constants */ /* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */

4
shared/radeon_state.c
View File

@ -201,6 +201,7 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
case RADEON_EMIT_PP_TEX_SIZE_0: case RADEON_EMIT_PP_TEX_SIZE_0:
case RADEON_EMIT_PP_TEX_SIZE_1: case RADEON_EMIT_PP_TEX_SIZE_1:
case RADEON_EMIT_PP_TEX_SIZE_2: case RADEON_EMIT_PP_TEX_SIZE_2:
case R200_EMIT_RB3D_BLENDCOLOR:
/* These packets don't contain memory offsets */ /* These packets don't contain memory offsets */
break; break;
@ -562,7 +563,8 @@ static struct {
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" }, { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
{ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
}; };