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nouveau: nv28 graph context init

main
Pekka Paalanen 2007-09-30 12:03:22 +03:00
parent 8ad605a264
commit aa2c337991
1 changed files with 156 additions and 4 deletions
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160
shared-core/nv30_graph.c
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@ -35,12 +35,162 @@
static void nv28_graph_context_init(struct drm_device *dev, static void nv28_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx) struct nouveau_gpuobj *ctx)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i; int i;
(void)dev; /*
write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements:
+0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
+0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
+0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000
+0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000
+0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303
+0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000
+0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8
+0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000
+0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000
+0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
+0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000
+0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d1c: 00000000 00000000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000);
INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000);
INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000);
INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101);
INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111);
INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080);
INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000);
INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001);
INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000);
INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000);
INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303);
INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303);
INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303);
INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303);
INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000);
INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000);
INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000);
INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000);
INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000);
INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000);
INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000);
INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000);
INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8);
INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8);
INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8);
INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8);
INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008);
INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008);
INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008);
INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008);
for (i=0; i<16; ++i)
INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000);
INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7ffff);
/*
write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements:
+0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0
+0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000
+0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000
+0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
...
+0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
...
+0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
+0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000
+0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080);
INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000);
INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040);
INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080);
INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0);
INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001);
INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000);
INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001);
INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000);
INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000);
for (i=0; i<0x880; i+=4) {
INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9);
INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c);
INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b);
INSTANCE_WR(ctx, (0x1b04/4)+i+3, 0x00000000);
} }
static void nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) /*
write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements:
+0x00742e24: 3f800000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x2704/4), 0x3f800000);
/*
write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements:
+0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
+0x00742e84: 00000000 bf800000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000);
INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000);
INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000);
INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000);
INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000);
INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000);
INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000);
/*
write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements:
+0x00742e34: 00000000 3f800000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000);
/*
write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements:
+0x00742e94: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements:
+0x00743804: 00000000 00000000 00000000 00000000
write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements:
+0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
*/
INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000);
/*
write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements:
+0x007437d4: 00000000 00000000 00000000 00000000
write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements:
+0x00743824: 00000000 000003f8 00000000 00000000
*/
INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8);
/* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */
INSTANCE_WR(ctx, 0x3468/4, 0x002fe000);
/*
write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements:
+0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
*/
for (i=0; i<8; ++i)
INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c);
}
static void nv30_31_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
int i; int i;
@ -933,7 +1083,8 @@ static void nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gp
INSTANCE_WR(ctx, 0x386c/4, 0xbf800000); INSTANCE_WR(ctx, 0x386c/4, 0xbf800000);
} }
static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) static void nv34_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
int i; int i;
@ -1826,7 +1977,8 @@ static void nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuob
INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000); INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000);
} }
static void nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) static void nv35_36_graph_context_init(struct drm_device *dev,
struct nouveau_gpuobj *ctx)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
int i; int i;