diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index a76ed8f9..e04613d3 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -178,7 +178,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_NONE 0 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 -#define DRM_FORMAT_MOD_VENDOR_NV 0x03 +#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 @@ -338,29 +338,17 @@ extern "C" { */ #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) -/* NVIDIA Tegra frame buffer modifiers */ - -/* - * Some modifiers take parameters, for example the number of vertical GOBs in - * a block. Reserve the lower 32 bits for parameters - */ -#define __fourcc_mod_tegra_mode_shift 32 -#define fourcc_mod_tegra_code(val, params) \ - fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) -#define fourcc_mod_tegra_mod(m) \ - (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) -#define fourcc_mod_tegra_param(m) \ - (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) +/* NVIDIA frame buffer modifiers */ /* * Tegra Tiled Layout, used by Tegra 2, 3 and 4. * * Pixels are arranged in simple tiles of 16 x 16 bytes. */ -#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) +#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) /* - * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 + * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later * * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked * vertically by a power of 2 (1 to 32 GOBs) to form a block. @@ -380,7 +368,21 @@ extern "C" { * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format * in full detail. */ -#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ + fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) + +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ + fourcc_mod_code(NVIDIA, 0x10) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ + fourcc_mod_code(NVIDIA, 0x11) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ + fourcc_mod_code(NVIDIA, 0x12) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ + fourcc_mod_code(NVIDIA, 0x13) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ + fourcc_mod_code(NVIDIA, 0x14) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ + fourcc_mod_code(NVIDIA, 0x15) /* * Broadcom VC4 "T" format diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index 0773bd02..fb9f15fc 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -278,20 +278,20 @@ static const char *modifier_to_string(uint64_t modifier) return "VIVANTE_SPLIT_TILED"; case DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED: return "VIVANTE_SPLIT_SUPER_TILED"; - case NV_FORMAT_MOD_TEGRA_TILED: - return "MOD_TEGRA_TILED"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): - return "MOD_TEGRA_16BX2_BLOCK(0)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(1): - return "MOD_TEGRA_16BX2_BLOCK(1)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(2): - return "MOD_TEGRA_16BX2_BLOCK(2)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(3): - return "MOD_TEGRA_16BX2_BLOCK(3)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(4): - return "MOD_TEGRA_16BX2_BLOCK(4)"; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(5): - return "MOD_TEGRA_16BX2_BLOCK(5)"; + case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED: + return "NVIDIA_TEGRA_TILED"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0): + return "NVIDIA_16BX2_BLOCK(0)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1): + return "NVIDIA_16BX2_BLOCK(1)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2): + return "NVIDIA_16BX2_BLOCK(2)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3): + return "NVIDIA_16BX2_BLOCK(3)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4): + return "NVIDIA_16BX2_BLOCK(4)"; + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5): + return "NVIDIA_16BX2_BLOCK(5)"; case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: return "MOD_BROADCOM_VC4_T_TILED"; default: