nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit.
parent
c8ee6a6cab
commit
ae883c97ad
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@ -63,24 +63,17 @@ nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = dev_priv->fifos[channel];
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uint32_t inst;
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DRM_DEBUG("ch%d\n", channel);
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if (IS_G80) {
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if (!chan->ramin)
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return -EINVAL;
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if (!chan->ramfc)
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return -EINVAL;
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NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
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(chan->ramin->instance >> 12) |
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NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
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} else {
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if (!chan->ramfc)
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return -EINVAL;
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NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
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(chan->ramfc->instance >> 8) |
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NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
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}
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if (IS_G80) inst = chan->ramfc->instance >> 12;
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else inst = chan->ramfc->instance >> 8;
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NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
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inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
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if (!nt) nv50_fifo_init_thingo(dev);
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return 0;
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@ -90,16 +83,13 @@ static void
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nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t inst;
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DRM_DEBUG("ch%d, nt=%d\n", channel, nt);
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if (IS_G80) {
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NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
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NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80);
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} else {
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NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
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NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84);
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}
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if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
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else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
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NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst);
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if (!nt) nv50_fifo_init_thingo(dev);
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}
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@ -234,7 +224,9 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
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if (IS_G80) {
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uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
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if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, ~0, 0x100,
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uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
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if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset,
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vram_offset, 0x100,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE,
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&ramfc, &chan->ramfc)))
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