Rewrite radeon_cp_dispatch_texture() to avoid pingponging back to userspace
when issue large (multi-buffer) uploads.main
Keith Whitwell
parent
a885d6786f
commit
b03fa556b2
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@ -1074,19 +1074,30 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
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const u8 *data;
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int size, dwords, tex_width, blit_width;
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u32 y, height;
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int ret = 0, i;
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int i;
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RING_LOCALS;
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dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
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/* FIXME: Be smarter about this...
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/* Flush the pixel cache. This ensures no pixel data gets mixed
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* up with the texture data from the host data blit, otherwise
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* part of the texture image may be corrupted.
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*/
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buf = radeon_freelist_get( dev );
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if ( !buf ) return DRM_ERR(EAGAIN);
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BEGIN_RING( 4 );
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RADEON_FLUSH_CACHE();
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RADEON_WAIT_UNTIL_IDLE();
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ADVANCE_RING();
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#ifdef __BIG_ENDIAN
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/* The Mesa texture functions provide the data in little endian as the
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* chip wants it, but we need to compensate for the fact that the CP
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* ring gets byte-swapped
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*/
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BEGIN_RING( 2 );
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OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
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ADVANCE_RING();
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#endif
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DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
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tex->offset >> 10, tex->pitch, tex->format,
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image->x, image->y, image->width, image->height );
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/* The compiler won't optimize away a division by a variable,
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* even if the only legal values are powers of two. Thus, we'll
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@ -1120,127 +1131,113 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
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return DRM_ERR(EINVAL);
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}
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DRM_DEBUG( " tex=%dx%d blit=%d\n",
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tex_width, tex->height, blit_width );
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DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width );
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/* Flush the pixel cache. This ensures no pixel data gets mixed
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* up with the texture data from the host data blit, otherwise
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* part of the texture image may be corrupted.
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*/
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BEGIN_RING( 4 );
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do {
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DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
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tex->offset >> 10, tex->pitch, tex->format,
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image->x, image->y, image->width, image->height );
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RADEON_FLUSH_CACHE();
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RADEON_WAIT_UNTIL_IDLE();
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ADVANCE_RING();
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#ifdef __BIG_ENDIAN
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/* The Mesa texture functions provide the data in little endian as the
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* chip wants it, but we need to compensate for the fact that the CP
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* ring gets byte-swapped
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*/
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BEGIN_RING( 2 );
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OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
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ADVANCE_RING();
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#endif
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/* Make a copy of the parameters in case we have to update them
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* for a multi-pass texture blit.
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*/
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y = image->y;
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height = image->height;
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data = (const u8 *)image->data;
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size = height * blit_width;
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if ( size > RADEON_MAX_TEXTURE_SIZE ) {
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/* Texture image is too large, do a multipass upload */
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ret = DRM_ERR(EAGAIN);
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/* Adjust the blit size to fit the indirect buffer */
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height = RADEON_MAX_TEXTURE_SIZE / blit_width;
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/* Make a copy of the parameters in case we have to
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* update them for a multi-pass texture blit.
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*/
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y = image->y;
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height = image->height;
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data = (const u8 *)image->data;
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size = height * blit_width;
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if ( size > RADEON_MAX_TEXTURE_SIZE ) {
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height = RADEON_MAX_TEXTURE_SIZE / blit_width;
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size = height * blit_width;
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} else if ( size < 4 && size > 0 ) {
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size = 4;
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} else if ( size == 0 ) {
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return 0;
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}
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/* Update the input parameters for next time */
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image->y += height;
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image->height -= height;
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image->data = (const char *)image->data + size;
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image->data += size;
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if ( DRM_COPY_TO_USER( tex->image, image, sizeof(*image) ) ) {
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DRM_ERROR( "EFAULT on tex->image\n" );
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return DRM_ERR(EFAULT);
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buf = radeon_freelist_get( dev );
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if ( 0 && !buf ) {
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radeon_do_cp_idle( dev_priv );
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buf = radeon_freelist_get( dev );
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}
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} else if ( size < 4 && size > 0 ) {
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size = 4;
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}
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dwords = size / 4;
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/* Dispatch the indirect buffer.
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*/
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buffer = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
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buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
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buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
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RADEON_GMC_BRUSH_NONE |
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(format << 8) |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_ROP3_S |
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RADEON_DP_SRC_SOURCE_HOST_DATA |
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RADEON_GMC_CLR_CMP_CNTL_DIS |
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RADEON_GMC_WR_MSK_DIS);
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buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
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buffer[3] = 0xffffffff;
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buffer[4] = 0xffffffff;
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buffer[5] = (y << 16) | image->x;
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buffer[6] = (height << 16) | image->width;
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buffer[7] = dwords;
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buffer += 8;
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if ( tex_width >= 32 ) {
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/* Texture image width is larger than the minimum, so we
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* can upload it directly.
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*/
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if ( DRM_COPY_FROM_USER( buffer, data, dwords * sizeof(u32) ) ) {
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DRM_ERROR( "EFAULT on data, %d dwords\n", dwords );
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return DRM_ERR(EFAULT);
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if ( !buf ) {
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DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
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DRM_COPY_TO_USER( tex->image, image, sizeof(*image) );
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return DRM_ERR(EAGAIN);
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}
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} else {
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/* Texture image width is less than the minimum, so we
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* need to pad out each image scanline to the minimum
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* width.
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/* Dispatch the indirect buffer.
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*/
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for ( i = 0 ; i < tex->height ; i++ ) {
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if ( DRM_COPY_FROM_USER( buffer, data, tex_width ) ) {
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DRM_ERROR( "EFAULT on pad, %d bytes\n",
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tex_width );
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buffer = (u32*)((char*)dev_priv->buffers->handle + buf->offset);
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dwords = size / 4;
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buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
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buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
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RADEON_GMC_BRUSH_NONE |
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(format << 8) |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_ROP3_S |
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RADEON_DP_SRC_SOURCE_HOST_DATA |
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RADEON_GMC_CLR_CMP_CNTL_DIS |
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RADEON_GMC_WR_MSK_DIS);
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buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
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buffer[3] = 0xffffffff;
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buffer[4] = 0xffffffff;
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buffer[5] = (y << 16) | image->x;
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buffer[6] = (height << 16) | image->width;
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buffer[7] = dwords;
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buffer += 8;
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if ( tex_width >= 32 ) {
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/* Texture image width is larger than the minimum, so we
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* can upload it directly.
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*/
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if ( DRM_COPY_FROM_USER( buffer, data,
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dwords * sizeof(u32) ) ) {
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DRM_ERROR( "EFAULT on data, %d dwords\n",
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dwords );
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return DRM_ERR(EFAULT);
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}
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buffer += 8;
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data += tex_width;
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} else {
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/* Texture image width is less than the minimum, so we
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* need to pad out each image scanline to the minimum
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* width.
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*/
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for ( i = 0 ; i < tex->height ; i++ ) {
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if ( DRM_COPY_FROM_USER( buffer, data,
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tex_width ) ) {
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DRM_ERROR( "EFAULT on pad, %d bytes\n",
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tex_width );
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return DRM_ERR(EFAULT);
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}
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buffer += 8;
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data += tex_width;
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}
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}
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}
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buf->pid = DRM_CURRENTPID;
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buf->used = (dwords + 8) * sizeof(u32);
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buf->pid = DRM_CURRENTPID;
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buf->used = (dwords + 8) * sizeof(u32);
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radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
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radeon_cp_discard_buffer( dev, buf );
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radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
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radeon_cp_discard_buffer( dev, buf );
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} while (image->height > 0);
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/* Flush the pixel cache after the blit completes. This ensures
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* the texture data is written out to memory before rendering
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* continues.
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*/
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BEGIN_RING( 4 );
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RADEON_FLUSH_CACHE();
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RADEON_WAIT_UNTIL_2D_IDLE();
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ADVANCE_RING();
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return ret;
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return 0;
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}
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@ -1074,19 +1074,30 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
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const u8 *data;
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int size, dwords, tex_width, blit_width;
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u32 y, height;
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int ret = 0, i;
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int i;
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RING_LOCALS;
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dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
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/* FIXME: Be smarter about this...
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/* Flush the pixel cache. This ensures no pixel data gets mixed
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* up with the texture data from the host data blit, otherwise
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* part of the texture image may be corrupted.
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*/
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buf = radeon_freelist_get( dev );
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if ( !buf ) return DRM_ERR(EAGAIN);
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BEGIN_RING( 4 );
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RADEON_FLUSH_CACHE();
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RADEON_WAIT_UNTIL_IDLE();
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ADVANCE_RING();
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#ifdef __BIG_ENDIAN
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/* The Mesa texture functions provide the data in little endian as the
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* chip wants it, but we need to compensate for the fact that the CP
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* ring gets byte-swapped
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*/
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BEGIN_RING( 2 );
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OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
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ADVANCE_RING();
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#endif
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DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
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tex->offset >> 10, tex->pitch, tex->format,
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image->x, image->y, image->width, image->height );
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/* The compiler won't optimize away a division by a variable,
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* even if the only legal values are powers of two. Thus, we'll
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@ -1120,127 +1131,113 @@ static int radeon_cp_dispatch_texture( drm_device_t *dev,
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return DRM_ERR(EINVAL);
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}
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DRM_DEBUG( " tex=%dx%d blit=%d\n",
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tex_width, tex->height, blit_width );
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DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width );
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/* Flush the pixel cache. This ensures no pixel data gets mixed
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* up with the texture data from the host data blit, otherwise
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* part of the texture image may be corrupted.
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*/
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BEGIN_RING( 4 );
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do {
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DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
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tex->offset >> 10, tex->pitch, tex->format,
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image->x, image->y, image->width, image->height );
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RADEON_FLUSH_CACHE();
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RADEON_WAIT_UNTIL_IDLE();
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ADVANCE_RING();
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#ifdef __BIG_ENDIAN
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/* The Mesa texture functions provide the data in little endian as the
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* chip wants it, but we need to compensate for the fact that the CP
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* ring gets byte-swapped
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*/
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BEGIN_RING( 2 );
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OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
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ADVANCE_RING();
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#endif
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/* Make a copy of the parameters in case we have to update them
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* for a multi-pass texture blit.
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*/
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y = image->y;
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height = image->height;
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data = (const u8 *)image->data;
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size = height * blit_width;
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if ( size > RADEON_MAX_TEXTURE_SIZE ) {
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/* Texture image is too large, do a multipass upload */
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ret = DRM_ERR(EAGAIN);
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/* Adjust the blit size to fit the indirect buffer */
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height = RADEON_MAX_TEXTURE_SIZE / blit_width;
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/* Make a copy of the parameters in case we have to
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* update them for a multi-pass texture blit.
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*/
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y = image->y;
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height = image->height;
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data = (const u8 *)image->data;
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size = height * blit_width;
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if ( size > RADEON_MAX_TEXTURE_SIZE ) {
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height = RADEON_MAX_TEXTURE_SIZE / blit_width;
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size = height * blit_width;
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} else if ( size < 4 && size > 0 ) {
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size = 4;
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} else if ( size == 0 ) {
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return 0;
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}
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/* Update the input parameters for next time */
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image->y += height;
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image->height -= height;
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image->data = (const char *)image->data + size;
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image->data += size;
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if ( DRM_COPY_TO_USER( tex->image, image, sizeof(*image) ) ) {
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DRM_ERROR( "EFAULT on tex->image\n" );
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return DRM_ERR(EFAULT);
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buf = radeon_freelist_get( dev );
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if ( 0 && !buf ) {
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radeon_do_cp_idle( dev_priv );
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buf = radeon_freelist_get( dev );
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}
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} else if ( size < 4 && size > 0 ) {
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size = 4;
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}
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dwords = size / 4;
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/* Dispatch the indirect buffer.
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*/
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buffer = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
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buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
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buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
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RADEON_GMC_BRUSH_NONE |
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(format << 8) |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_ROP3_S |
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RADEON_DP_SRC_SOURCE_HOST_DATA |
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RADEON_GMC_CLR_CMP_CNTL_DIS |
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RADEON_GMC_WR_MSK_DIS);
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buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
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buffer[3] = 0xffffffff;
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buffer[4] = 0xffffffff;
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buffer[5] = (y << 16) | image->x;
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buffer[6] = (height << 16) | image->width;
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buffer[7] = dwords;
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buffer += 8;
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if ( tex_width >= 32 ) {
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/* Texture image width is larger than the minimum, so we
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* can upload it directly.
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*/
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if ( DRM_COPY_FROM_USER( buffer, data, dwords * sizeof(u32) ) ) {
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DRM_ERROR( "EFAULT on data, %d dwords\n", dwords );
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return DRM_ERR(EFAULT);
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if ( !buf ) {
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DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
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DRM_COPY_TO_USER( tex->image, image, sizeof(*image) );
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return DRM_ERR(EAGAIN);
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}
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} else {
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/* Texture image width is less than the minimum, so we
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* need to pad out each image scanline to the minimum
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* width.
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/* Dispatch the indirect buffer.
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*/
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for ( i = 0 ; i < tex->height ; i++ ) {
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if ( DRM_COPY_FROM_USER( buffer, data, tex_width ) ) {
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DRM_ERROR( "EFAULT on pad, %d bytes\n",
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tex_width );
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buffer = (u32*)((char*)dev_priv->buffers->handle + buf->offset);
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dwords = size / 4;
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buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
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buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
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RADEON_GMC_BRUSH_NONE |
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(format << 8) |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_ROP3_S |
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RADEON_DP_SRC_SOURCE_HOST_DATA |
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RADEON_GMC_CLR_CMP_CNTL_DIS |
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RADEON_GMC_WR_MSK_DIS);
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buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
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buffer[3] = 0xffffffff;
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buffer[4] = 0xffffffff;
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buffer[5] = (y << 16) | image->x;
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buffer[6] = (height << 16) | image->width;
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buffer[7] = dwords;
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buffer += 8;
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if ( tex_width >= 32 ) {
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/* Texture image width is larger than the minimum, so we
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* can upload it directly.
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*/
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if ( DRM_COPY_FROM_USER( buffer, data,
|
||||
dwords * sizeof(u32) ) ) {
|
||||
DRM_ERROR( "EFAULT on data, %d dwords\n",
|
||||
dwords );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
buffer += 8;
|
||||
data += tex_width;
|
||||
} else {
|
||||
/* Texture image width is less than the minimum, so we
|
||||
* need to pad out each image scanline to the minimum
|
||||
* width.
|
||||
*/
|
||||
for ( i = 0 ; i < tex->height ; i++ ) {
|
||||
if ( DRM_COPY_FROM_USER( buffer, data,
|
||||
tex_width ) ) {
|
||||
DRM_ERROR( "EFAULT on pad, %d bytes\n",
|
||||
tex_width );
|
||||
return DRM_ERR(EFAULT);
|
||||
}
|
||||
buffer += 8;
|
||||
data += tex_width;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
buf->pid = DRM_CURRENTPID;
|
||||
buf->used = (dwords + 8) * sizeof(u32);
|
||||
buf->pid = DRM_CURRENTPID;
|
||||
buf->used = (dwords + 8) * sizeof(u32);
|
||||
radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
|
||||
radeon_cp_discard_buffer( dev, buf );
|
||||
|
||||
radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
|
||||
radeon_cp_discard_buffer( dev, buf );
|
||||
} while (image->height > 0);
|
||||
|
||||
/* Flush the pixel cache after the blit completes. This ensures
|
||||
* the texture data is written out to memory before rendering
|
||||
* continues.
|
||||
*/
|
||||
BEGIN_RING( 4 );
|
||||
|
||||
RADEON_FLUSH_CACHE();
|
||||
RADEON_WAIT_UNTIL_2D_IDLE();
|
||||
|
||||
ADVANCE_RING();
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue