radeon: add some more r100 support to test AGP
parent
40c64eb524
commit
b09cb93e2d
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@ -356,6 +356,9 @@ void r300_init_reg_flags(struct drm_device *dev)
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} else {
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ADD_RANGE(RADEON_SE_COORD_FMT, 1);
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ADD_RANGE(RADEON_SE_CNTL_STATUS, 1);
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ADD_RANGE(RADEON_PP_TXFILTER_0, 1);
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ADD_RANGE(RADEON_PP_TXFORMAT_0, 1);
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ADD_RANGE(RADEON_PP_TEX_SIZE_0, 1);
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@ -122,7 +122,7 @@ static __inline__ int radeon_cs_relocate_packet0(struct drm_device *dev, struct
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/* this is too strict we may want to expand the length in the future and have
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old kernels ignore it. */
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if (packet3_hdr != (RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16))) {
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DRM_ERROR("Packet 3 was %x should have been %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16));
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DRM_ERROR("Packet 3 was %x should have been %x: reg is %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16), reg);
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return -EINVAL;
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}
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@ -195,30 +195,6 @@ static int radeon_cs_relocate_packet3(struct drm_device *dev, struct drm_file *f
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return 0;
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}
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static __inline__ int radeon_cs_check_offset(struct drm_device *dev,
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uint32_t reg, uint32_t val)
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{
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uint32_t offset;
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switch(reg) {
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case RADEON_DST_PITCH_OFFSET:
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case RADEON_SRC_PITCH_OFFSET:
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offset = val & ((1 << 22) - 1);
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offset <<= 10;
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break;
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case R300_RB3D_COLOROFFSET0:
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case R300_ZB_DEPTHOFFSET:
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offset = val;
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break;
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case R300_TX_OFFSET_0:
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case R300_TX_OFFSET_0+4:
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offset = val & 0xffffffe0;
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break;
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}
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return 0;
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}
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int radeon_cs_packet0(struct drm_device *dev, struct drm_file *file_priv,
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uint32_t *packets, uint32_t offset_dw)
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{
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@ -308,6 +284,7 @@ int radeon_cs_parse(struct drm_device *dev, struct drm_file *file_priv,
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DRM_ERROR("need relocate packet 3 for %x\n", reg);
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break;
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case RADEON_3D_DRAW_IMMD: /* triggers drawing using in-packet vertex data */
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case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
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case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
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case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
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