set bracing style like Linux
parent
a5cf4cc369
commit
b49b3ba4c1
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@ -254,8 +254,7 @@ bool drm_crtc_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
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/* Now, enable the clocks, plane, pipe, and outputs that we set up. */
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crtc->funcs->commit(crtc);
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list_for_each_entry(output, &dev->mode_config.output_list, head) {
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if (output->crtc == crtc)
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{
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if (output->crtc == crtc) {
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output->funcs->commit(output);
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#if 0 // TODO def RANDR_12_INTERFACE
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if (output->randr_output)
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@ -624,8 +623,7 @@ int drm_crtc_set_config(struct drm_crtc *crtc, struct drm_mode_crtc *crtc_info,
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else
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new_crtc = output->crtc;
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for (ro = 0; ro < crtc_info->count_outputs; ro++)
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{
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for (ro = 0; ro < crtc_info->count_outputs; ro++) {
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if (output_set[ro] == output)
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new_crtc = crtc;
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}
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@ -913,8 +911,7 @@ int drm_mode_setcrtc(struct inode *inode, struct file *filp,
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return -EFAULT;
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crtc = idr_find(&dev->mode_config.crtc_idr, crtc_req.crtc_id);
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if (!crtc || (crtc->id != crtc_req.crtc_id))
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{
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if (!crtc || (crtc->id != crtc_req.crtc_id)) {
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DRM_DEBUG("Unknown CRTC ID %d\n", crtc_req.crtc_id);
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return -EINVAL;
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}
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@ -930,15 +927,12 @@ int drm_mode_setcrtc(struct inode *inode, struct file *filp,
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}
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}
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mode = idr_find(&dev->mode_config.crtc_idr, crtc_req.mode);
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if (!mode || (mode->mode_id != crtc_req.mode))
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{
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{
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struct drm_output *output;
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list_for_each_entry(output, &dev->mode_config.output_list, head) {
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list_for_each_entry(mode, &output->modes, head) {
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drm_mode_debug_printmodeline(dev, mode);
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}
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if (!mode || (mode->mode_id != crtc_req.mode)) {
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struct drm_output *output;
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list_for_each_entry(output, &dev->mode_config.output_list, head) {
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list_for_each_entry(mode, &output->modes, head) {
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drm_mode_debug_printmodeline(dev, mode);
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}
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}
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@ -412,8 +412,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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case DPMSModeSuspend:
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/* Enable the DPLL */
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temp = I915_READ(dpll_reg);
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if ((temp & DPLL_VCO_ENABLE) == 0)
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{
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if ((temp & DPLL_VCO_ENABLE) == 0) {
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I915_WRITE(dpll_reg, temp);
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I915_READ(dpll_reg);
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/* Wait for the clocks to stabilize. */
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@ -435,8 +434,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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/* Enable the plane */
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temp = I915_READ(dspcntr_reg);
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if ((temp & DISPLAY_PLANE_ENABLE) == 0)
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{
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if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
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I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
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@ -456,8 +454,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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/* Disable display plane */
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temp = I915_READ(dspcntr_reg);
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if ((temp & DISPLAY_PLANE_ENABLE) != 0)
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{
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if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
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I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
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@ -719,11 +716,9 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo)
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{
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if (is_sdvo) {
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dpll |= DPLL_DVO_HIGH_SPEED;
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if (IS_I945G(dev) || IS_I945GM(dev))
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{
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if (IS_I945G(dev) || IS_I945GM(dev)) {
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int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
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dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
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}
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@ -760,8 +755,7 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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if (is_tv)
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{
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if (is_tv) {
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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@ -801,8 +795,7 @@ static void intel_crtc_mode_set(struct drm_crtc *crtc,
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dspcntr |= DISPPLANE_SEL_PIPE_B;
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pipeconf = I915_READ(pipeconf_reg);
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if (pipe == 0 && !IS_I965G(dev))
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{
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if (pipe == 0 && !IS_I965G(dev)) {
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/* Enable pixel doubling when the dot clock is > 90% of the (display)
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* core speed.
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*
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Reference in New Issue