drm: add initial rs690 support for drm.
This adds support for configuring the RS690 GART.main
parent
6bfb9b639a
commit
b8755ff7c3
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@ -232,6 +232,7 @@
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0x1002 0x7297 CHIP_RV560|RADEON_NEW_MEMMAP "ATI RV560"
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0x1002 0x7834 CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP "ATI Radeon RS350 9000/9100 IGP"
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0x1002 0x7835 CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Radeon RS350 Mobility IGP"
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0x1002 0x791e CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART "ATI Radeon RS690 X1250 IGP"
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[r128]
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0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"
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@ -825,11 +825,19 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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return ret;
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}
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static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
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{
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RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
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return RADEON_READ(RS690_MC_DATA);
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}
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u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
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return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
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else
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@ -840,6 +848,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
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RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
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else
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@ -850,6 +860,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
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{
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
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RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
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else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
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RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
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else
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@ -1362,6 +1374,74 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
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}
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}
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/* Enable or disable RS690 GART on the chip */
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static void radeon_set_rs690gart(drm_radeon_private_t * dev_priv, int on)
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{
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u32 temp;
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if (on) {
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DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n",
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dev_priv->gart_vm_start,
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(long)dev_priv->gart_info.bus_addr,
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dev_priv->gart_size);
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temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL);
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RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000);
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RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
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RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
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temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID);
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RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800);
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RS690_WRITE_MCIND(RS690_MC_GART_BASE,
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dev_priv->gart_info.bus_addr);
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temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL);
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RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000);
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RS690_WRITE_MCIND(RS690_MC_AGP_BASE,
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(unsigned int)dev_priv->gart_vm_start);
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dev_priv->gart_size = 32*1024*1024;
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temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
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0xffff0000) | (dev_priv->gart_vm_start >> 16));
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RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp);
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temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE);
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RS690_WRITE_MCIND(RS690_MC_AGP_SIZE,
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RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB);
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do
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{
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temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
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if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
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RS690_MC_GART_CLEAR_DONE)
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break;
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DRM_UDELAY(1);
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} while(1);
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RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
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RS690_MC_GART_CC_CLEAR);
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do
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{
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temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL);
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if ((temp & RS690_MC_GART_CLEAR_STATUS) ==
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RS690_MC_GART_CLEAR_DONE)
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break;
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DRM_UDELAY(1);
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} while(1);
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RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL,
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RS690_MC_GART_CC_NO_CHANGE);
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}
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else
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{
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RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS);
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}
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}
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static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
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{
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u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
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@ -1396,6 +1476,12 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
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{
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u32 tmp;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
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{
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radeon_set_rs690gart(dev_priv, on);
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return;
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}
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if (dev_priv->flags & RADEON_IS_IGPGART) {
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radeon_set_igpgart(dev_priv, on);
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return;
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@ -124,6 +124,7 @@ enum radeon_family {
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CHIP_R420,
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CHIP_RV410,
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CHIP_RS400,
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CHIP_RS690,
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CHIP_RV515,
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CHIP_R520,
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CHIP_RV530,
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@ -471,6 +472,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
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#define RADEON_IGPGART_ENABLE 0x38
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#define RADEON_IGPGART_UNK_39 0x39
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#define RS690_MC_INDEX 0x78
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# define RS690_MC_INDEX_MASK 0x1ff
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# define RS690_MC_INDEX_WR_EN (1 << 9)
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# define RS690_MC_INDEX_WR_ACK 0x7f
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#define RS690_MC_DATA 0x7c
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#define RS690_MC_MISC_CNTL 0x18
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#define RS690_MC_GART_FEATURE_ID 0x2b
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#define RS690_MC_GART_BASE 0x2c
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#define RS690_MC_GART_CACHE_CNTL 0x2e
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# define RS690_MC_GART_CC_NO_CHANGE 0x0
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# define RS690_MC_GART_CC_CLEAR 0x1
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# define RS690_MC_GART_CLEAR_STATUS (1 << 1)
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# define RS690_MC_GART_CLEAR_DONE (0 << 1)
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# define RS690_MC_GART_CLEAR_PENDING (1 << 1)
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#define RS690_MC_AGP_SIZE 0x38
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# define RS690_MC_GART_DIS 0x0
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# define RS690_MC_GART_EN 0x1
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# define RS690_MC_AGP_SIZE_32MB (0 << 1)
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# define RS690_MC_AGP_SIZE_64MB (1 << 1)
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# define RS690_MC_AGP_SIZE_128MB (2 << 1)
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# define RS690_MC_AGP_SIZE_256MB (3 << 1)
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# define RS690_MC_AGP_SIZE_512MB (4 << 1)
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# define RS690_MC_AGP_SIZE_1GB (5 << 1)
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# define RS690_MC_AGP_SIZE_2GB (6 << 1)
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#define RS690_MC_AGP_MODE_CONTROL 0x39
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#define RS690_MC_FB_LOCATION 0x100
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#define RS690_MC_AGP_LOCATION 0x101
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#define RS690_MC_AGP_BASE 0x102
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#define R520_MC_IND_INDEX 0x70
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#define R520_MC_IND_WR_EN (1<<24)
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#define R520_MC_IND_DATA 0x74
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@ -1082,8 +1113,8 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
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#define RADEON_PCIGART_TABLE_SIZE (32*1024)
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#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
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#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
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#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
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#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
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#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
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#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
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@ -1116,6 +1147,13 @@ do { \
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RADEON_WRITE(R520_MC_IND_INDEX, 0); \
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} while (0)
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#define RS690_WRITE_MCIND( addr, val ) \
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do { \
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RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
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RADEON_WRITE(RS690_MC_DATA, val); \
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RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
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} while (0)
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#define CP_PACKET0( reg, n ) \
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(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
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#define CP_PACKET0_TABLE( reg, n ) \
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