Remove mask parameter from radeon_acknowledge_irqs().
Simply always acknowledge all interrupts we're interested in, to avoid hard hangs when an unexpected interrupt is flagged.main
parent
24c09faec1
commit
b8dd314875
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@ -81,13 +81,15 @@ void radeon_disable_vblank(drm_device_t *dev, int crtc)
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}
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}
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}
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}
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static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
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static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv)
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u32 mask)
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{
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{
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u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) &
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u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) &
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(mask | RADEON_CRTC_VBLANK_MASK | RADEON_CRTC2_VBLANK_MASK);
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(RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
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RADEON_CRTC2_VBLANK_STAT);
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if (irqs)
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if (irqs)
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RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
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RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
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return irqs;
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return irqs;
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}
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}
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@ -119,10 +121,12 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
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/* Only consider the bits we're interested in - others could be used
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/* Only consider the bits we're interested in - others could be used
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* outside the DRM
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* outside the DRM
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*/
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*/
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stat = radeon_acknowledge_irqs(dev_priv, dev_priv->irq_enable_reg);
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stat = radeon_acknowledge_irqs(dev_priv);
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if (!stat)
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if (!stat)
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return IRQ_NONE;
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return IRQ_NONE;
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stat &= dev_priv->irq_enable_reg;
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/* SW interrupt */
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/* SW interrupt */
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if (stat & RADEON_SW_INT_TEST)
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if (stat & RADEON_SW_INT_TEST)
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DRM_WAKEUP(&dev_priv->swi_queue);
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DRM_WAKEUP(&dev_priv->swi_queue);
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@ -247,9 +251,7 @@ void radeon_driver_irq_preinstall(drm_device_t * dev)
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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/* Clear bits if they're already high */
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/* Clear bits if they're already high */
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radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
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radeon_acknowledge_irqs(dev_priv);
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RADEON_CRTC_VBLANK_STAT |
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RADEON_CRTC2_VBLANK_STAT));
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}
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}
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int radeon_driver_irq_postinstall(drm_device_t * dev)
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int radeon_driver_irq_postinstall(drm_device_t * dev)
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