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radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI. 

Another corner case that isn't well-explained yet.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
main
Michel Dänzer 2012-09-05 18:44:45 +02:00 committed by Michel Dänzer
parent 45083e6d36
commit b925022a3e
1 changed files with 8 additions and 3 deletions
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11
radeon/radeon_surface.c
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@ -974,10 +974,15 @@ static void si_surf_minify_linear_aligned(struct radeon_surface *surf,
surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
}
/* XXX: Second smallest level uses larger pitch, not sure of the real reason,
* my best guess so far: rows evenly distributed across slice
/* XXX: Texture sampling uses unexpectedly large pitches in some cases,
* these are just guesses for the rules behind those
*/
xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y);
if (level == 0 && surf->last_level == 0)
/* Non-mipmap pitch padded to slice alignment */
xalign = MAX2(xalign, slice_align / surf->bpe);
else
/* Small rows evenly distributed across slice */
xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y);
surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign);
surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign);