radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.
Another corner case that isn't well-explained yet. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>main
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@ -974,9 +974,14 @@ static void si_surf_minify_linear_aligned(struct radeon_surface *surf,
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surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
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}
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/* XXX: Second smallest level uses larger pitch, not sure of the real reason,
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* my best guess so far: rows evenly distributed across slice
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/* XXX: Texture sampling uses unexpectedly large pitches in some cases,
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* these are just guesses for the rules behind those
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*/
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if (level == 0 && surf->last_level == 0)
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/* Non-mipmap pitch padded to slice alignment */
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xalign = MAX2(xalign, slice_align / surf->bpe);
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else
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/* Small rows evenly distributed across slice */
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xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y);
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surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign);
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