nouveau: nv04 context switching support. Works for starting X up at least.
Stephane Marchesin
parent
69b11f44f0
commit
bac3f49daa
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@ -27,262 +27,321 @@
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#include "nouveau_drm.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drv.h"
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struct reg_interval
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static uint32_t nv04_graph_ctx_regs [] = {
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{
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NV04_PGRAPH_CTX_SWITCH1,
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uint32_t reg;
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NV04_PGRAPH_CTX_SWITCH2,
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int number;
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NV04_PGRAPH_CTX_SWITCH3,
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} nv04_graph_ctx_regs [] = {
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NV04_PGRAPH_CTX_SWITCH4,
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{NV04_PGRAPH_CTX_SWITCH1,1},
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NV04_PGRAPH_CTX_CACHE1,
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{NV04_PGRAPH_CTX_SWITCH2,1},
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NV04_PGRAPH_CTX_CACHE2,
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{NV04_PGRAPH_CTX_SWITCH3,1},
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NV04_PGRAPH_CTX_CACHE3,
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{NV04_PGRAPH_CTX_SWITCH4,1},
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NV04_PGRAPH_CTX_CACHE4,
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{NV04_PGRAPH_CTX_CACHE1,1},
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0x00400184,
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{NV04_PGRAPH_CTX_CACHE2,1},
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0x004001a4,
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{NV04_PGRAPH_CTX_CACHE3,1},
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0x004001c4,
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{NV04_PGRAPH_CTX_CACHE4,1},
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0x004001e4,
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{0x00400184,1},
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0x00400188,
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{0x004001a4,1},
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0x004001a8,
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{0x004001c4,1},
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0x004001c8,
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{0x004001e4,1},
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0x004001e8,
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{0x00400188,1},
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0x0040018c,
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{0x004001a8,1},
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0x004001ac,
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{0x004001c8,1},
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0x004001cc,
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{0x004001e8,1},
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0x004001ec,
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{0x0040018c,1},
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0x00400190,
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{0x004001ac,1},
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0x004001b0,
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{0x004001cc,1},
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0x004001d0,
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{0x004001ec,1},
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0x004001f0,
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{0x00400190,1},
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0x00400194,
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{0x004001b0,1},
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0x004001b4,
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{0x004001d0,1},
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0x004001d4,
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{0x004001f0,1},
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0x004001f4,
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{0x00400194,1},
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0x00400198,
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{0x004001b4,1},
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0x004001b8,
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{0x004001d4,1},
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0x004001d8,
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{0x004001f4,1},
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0x004001f8,
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{0x00400198,1},
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0x0040019c,
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{0x004001b8,1},
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0x004001bc,
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{0x004001d8,1},
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0x004001dc,
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{0x004001f8,1},
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0x004001fc,
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{0x0040019c,1},
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0x00400174,
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{0x004001bc,1},
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NV04_PGRAPH_DMA_START_0,
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{0x004001dc,1},
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NV04_PGRAPH_DMA_START_1,
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{0x004001fc,1},
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NV04_PGRAPH_DMA_LENGTH,
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{0x00400174,1},
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NV04_PGRAPH_DMA_MISC,
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{NV04_PGRAPH_DMA_START_0,1},
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NV04_PGRAPH_DMA_PITCH,
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{NV04_PGRAPH_DMA_START_1,1},
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NV04_PGRAPH_BOFFSET0,
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{NV04_PGRAPH_DMA_LENGTH,1},
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NV04_PGRAPH_BBASE0,
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{NV04_PGRAPH_DMA_MISC,1},
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NV04_PGRAPH_BLIMIT0,
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{NV04_PGRAPH_DMA_PITCH,1},
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NV04_PGRAPH_BOFFSET1,
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{NV04_PGRAPH_BOFFSET0,1},
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NV04_PGRAPH_BBASE1,
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{NV04_PGRAPH_BBASE0,1},
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NV04_PGRAPH_BLIMIT1,
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{NV04_PGRAPH_BLIMIT0,1},
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NV04_PGRAPH_BOFFSET2,
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{NV04_PGRAPH_BOFFSET1,1},
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NV04_PGRAPH_BBASE2,
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{NV04_PGRAPH_BBASE1,1},
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NV04_PGRAPH_BLIMIT2,
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{NV04_PGRAPH_BLIMIT1,1},
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NV04_PGRAPH_BOFFSET3,
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{NV04_PGRAPH_BOFFSET2,1},
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NV04_PGRAPH_BBASE3,
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{NV04_PGRAPH_BBASE2,1},
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NV04_PGRAPH_BLIMIT3,
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{NV04_PGRAPH_BLIMIT2,1},
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NV04_PGRAPH_BOFFSET4,
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{NV04_PGRAPH_BOFFSET3,1},
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NV04_PGRAPH_BBASE4,
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{NV04_PGRAPH_BBASE3,1},
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NV04_PGRAPH_BLIMIT4,
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{NV04_PGRAPH_BLIMIT3,1},
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NV04_PGRAPH_BOFFSET5,
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{NV04_PGRAPH_BOFFSET4,1},
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NV04_PGRAPH_BBASE5,
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{NV04_PGRAPH_BBASE4,1},
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NV04_PGRAPH_BLIMIT5,
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{NV04_PGRAPH_BLIMIT4,1},
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NV04_PGRAPH_BPITCH0,
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{NV04_PGRAPH_BOFFSET5,1},
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NV04_PGRAPH_BPITCH1,
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{NV04_PGRAPH_BBASE5,1},
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NV04_PGRAPH_BPITCH2,
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{NV04_PGRAPH_BLIMIT5,1},
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NV04_PGRAPH_BPITCH3,
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{NV04_PGRAPH_BPITCH0,1},
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NV04_PGRAPH_BPITCH4,
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{NV04_PGRAPH_BPITCH1,1},
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NV04_PGRAPH_SURFACE,
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{NV04_PGRAPH_BPITCH2,1},
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NV04_PGRAPH_STATE,
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{NV04_PGRAPH_BPITCH3,1},
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NV04_PGRAPH_BSWIZZLE2,
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{NV04_PGRAPH_BPITCH4,1},
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NV04_PGRAPH_BSWIZZLE5,
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{NV04_PGRAPH_SURFACE,1},
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NV04_PGRAPH_BPIXEL,
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{NV04_PGRAPH_STATE,1},
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NV04_PGRAPH_NOTIFY,
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{NV04_PGRAPH_BSWIZZLE2,1},
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NV04_PGRAPH_PATT_COLOR0,
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{NV04_PGRAPH_BSWIZZLE5,1},
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NV04_PGRAPH_PATT_COLOR1,
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{NV04_PGRAPH_BPIXEL,1},
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NV04_PGRAPH_PATT_COLORRAM+0x00,
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{NV04_PGRAPH_NOTIFY,1},
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NV04_PGRAPH_PATT_COLORRAM+0x01,
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{NV04_PGRAPH_PATT_COLOR0,1},
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NV04_PGRAPH_PATT_COLORRAM+0x02,
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{NV04_PGRAPH_PATT_COLOR1,1},
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NV04_PGRAPH_PATT_COLORRAM+0x03,
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{NV04_PGRAPH_PATT_COLORRAM,64},
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NV04_PGRAPH_PATT_COLORRAM+0x04,
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{NV04_PGRAPH_PATTERN,1},
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NV04_PGRAPH_PATT_COLORRAM+0x05,
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{0x0040080c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x06,
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{NV04_PGRAPH_PATTERN_SHAPE,1},
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NV04_PGRAPH_PATT_COLORRAM+0x07,
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{0x00400600,1},
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NV04_PGRAPH_PATT_COLORRAM+0x08,
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{NV04_PGRAPH_ROP3,1},
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NV04_PGRAPH_PATT_COLORRAM+0x09,
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{NV04_PGRAPH_CHROMA,1},
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NV04_PGRAPH_PATT_COLORRAM+0x0A,
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{NV04_PGRAPH_BETA_AND,1},
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NV04_PGRAPH_PATT_COLORRAM+0x0B,
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{NV04_PGRAPH_BETA_PREMULT,1},
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NV04_PGRAPH_PATT_COLORRAM+0x0C,
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{NV04_PGRAPH_CONTROL0,1},
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NV04_PGRAPH_PATT_COLORRAM+0x0D,
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{NV04_PGRAPH_CONTROL1,1},
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NV04_PGRAPH_PATT_COLORRAM+0x0E,
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{NV04_PGRAPH_CONTROL2,1},
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NV04_PGRAPH_PATT_COLORRAM+0x0F,
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{NV04_PGRAPH_BLEND,1},
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NV04_PGRAPH_PATT_COLORRAM+0x10,
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{NV04_PGRAPH_STORED_FMT,1},
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NV04_PGRAPH_PATT_COLORRAM+0x11,
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{NV04_PGRAPH_SOURCE_COLOR,1},
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NV04_PGRAPH_PATT_COLORRAM+0x12,
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{0x00400560,1},
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NV04_PGRAPH_PATT_COLORRAM+0x13,
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{0x00400568,1},
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NV04_PGRAPH_PATT_COLORRAM+0x14,
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{0x00400564,1},
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NV04_PGRAPH_PATT_COLORRAM+0x15,
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{0x0040056c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x16,
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{0x00400400,1},
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NV04_PGRAPH_PATT_COLORRAM+0x17,
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{0x00400480,1},
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NV04_PGRAPH_PATT_COLORRAM+0x18,
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{0x00400404,1},
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NV04_PGRAPH_PATT_COLORRAM+0x19,
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{0x00400484,1},
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NV04_PGRAPH_PATT_COLORRAM+0x1A,
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{0x00400408,1},
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NV04_PGRAPH_PATT_COLORRAM+0x1B,
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{0x00400488,1},
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NV04_PGRAPH_PATT_COLORRAM+0x1C,
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{0x0040040c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x1D,
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{0x0040048c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x1E,
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{0x00400410,1},
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NV04_PGRAPH_PATT_COLORRAM+0x1F,
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{0x00400490,1},
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NV04_PGRAPH_PATT_COLORRAM+0x20,
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{0x00400414,1},
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NV04_PGRAPH_PATT_COLORRAM+0x21,
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{0x00400494,1},
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NV04_PGRAPH_PATT_COLORRAM+0x22,
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{0x00400418,1},
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NV04_PGRAPH_PATT_COLORRAM+0x23,
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{0x00400498,1},
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NV04_PGRAPH_PATT_COLORRAM+0x24,
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{0x0040041c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x25,
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{0x0040049c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x26,
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{0x00400420,1},
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NV04_PGRAPH_PATT_COLORRAM+0x27,
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{0x004004a0,1},
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NV04_PGRAPH_PATT_COLORRAM+0x28,
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{0x00400424,1},
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NV04_PGRAPH_PATT_COLORRAM+0x29,
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{0x004004a4,1},
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NV04_PGRAPH_PATT_COLORRAM+0x2A,
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{0x00400428,1},
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NV04_PGRAPH_PATT_COLORRAM+0x2B,
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{0x004004a8,1},
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NV04_PGRAPH_PATT_COLORRAM+0x2C,
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{0x0040042c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x2D,
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{0x004004ac,1},
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NV04_PGRAPH_PATT_COLORRAM+0x2E,
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{0x00400430,1},
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NV04_PGRAPH_PATT_COLORRAM+0x2F,
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{0x004004b0,1},
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NV04_PGRAPH_PATT_COLORRAM+0x30,
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{0x00400434,1},
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NV04_PGRAPH_PATT_COLORRAM+0x31,
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{0x004004b4,1},
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NV04_PGRAPH_PATT_COLORRAM+0x32,
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{0x00400438,1},
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NV04_PGRAPH_PATT_COLORRAM+0x33,
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{0x004004b8,1},
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NV04_PGRAPH_PATT_COLORRAM+0x34,
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{0x0040043c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x35,
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{0x004004bc,1},
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NV04_PGRAPH_PATT_COLORRAM+0x36,
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{0x00400440,1},
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NV04_PGRAPH_PATT_COLORRAM+0x37,
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{0x004004c0,1},
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NV04_PGRAPH_PATT_COLORRAM+0x38,
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{0x00400444,1},
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NV04_PGRAPH_PATT_COLORRAM+0x39,
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{0x004004c4,1},
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NV04_PGRAPH_PATT_COLORRAM+0x3A,
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{0x00400448,1},
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NV04_PGRAPH_PATT_COLORRAM+0x3B,
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{0x004004c8,1},
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NV04_PGRAPH_PATT_COLORRAM+0x3C,
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{0x0040044c,1},
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NV04_PGRAPH_PATT_COLORRAM+0x3D,
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{0x004004cc,1},
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NV04_PGRAPH_PATT_COLORRAM+0x3E,
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{0x00400450,1},
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NV04_PGRAPH_PATT_COLORRAM+0x3F,
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{0x004004d0,1},
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NV04_PGRAPH_PATTERN,
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{0x00400454,1},
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0x0040080c,
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{0x004004d4,1},
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NV04_PGRAPH_PATTERN_SHAPE,
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{0x00400458,1},
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0x00400600,
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{0x004004d8,1},
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NV04_PGRAPH_ROP3,
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{0x0040045c,1},
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NV04_PGRAPH_CHROMA,
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{0x004004dc,1},
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NV04_PGRAPH_BETA_AND,
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{0x00400460,1},
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NV04_PGRAPH_BETA_PREMULT,
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{0x004004e0,1},
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NV04_PGRAPH_CONTROL0,
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{0x00400464,1},
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NV04_PGRAPH_CONTROL1,
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{0x004004e4,1},
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NV04_PGRAPH_CONTROL2,
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{0x00400468,1},
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NV04_PGRAPH_BLEND,
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{0x004004e8,1},
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NV04_PGRAPH_STORED_FMT,
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{0x0040046c,1},
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NV04_PGRAPH_SOURCE_COLOR,
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{0x004004ec,1},
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0x00400560,
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{0x00400470,1},
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0x00400568,
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{0x004004f0,1},
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0x00400564,
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{0x00400474,1},
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0x0040056c,
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{0x004004f4,1},
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0x00400400,
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{0x00400478,1},
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0x00400480,
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{0x004004f8,1},
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0x00400404,
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{0x0040047c,1},
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0x00400484,
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{0x004004fc,1},
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0x00400408,
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{0x0040053c,1},
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0x00400488,
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{0x00400544,1},
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0x0040040c,
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{0x00400540,1},
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0x0040048c,
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{0x00400548,1},
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0x00400410,
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{0x00400560,1},
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0x00400490,
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{0x00400568,1},
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0x00400414,
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{0x00400564,1},
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0x00400494,
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{0x0040056c,1},
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0x00400418,
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{0x00400534,1},
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0x00400498,
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{0x00400538,1},
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0x0040041c,
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{0x00400514,1},
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0x0040049c,
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{0x00400518,1},
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0x00400420,
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{0x0040051c,1},
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0x004004a0,
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{0x00400520,1},
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0x00400424,
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{0x00400524,1},
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0x004004a4,
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{0x00400528,1},
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0x00400428,
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{0x0040052c,1},
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0x004004a8,
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{0x00400530,1},
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0x0040042c,
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{0x00400d00,1},
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0x004004ac,
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{0x00400d40,1},
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0x00400430,
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{0x00400d80,1},
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0x004004b0,
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{0x00400d04,1},
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0x00400434,
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{0x00400d44,1},
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0x004004b4,
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{0x00400d84,1},
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0x00400438,
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{0x00400d08,1},
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0x004004b8,
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{0x00400d48,1},
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0x0040043c,
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{0x00400d88,1},
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0x004004bc,
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{0x00400d0c,1},
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0x00400440,
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{0x00400d4c,1},
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0x004004c0,
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{0x00400d8c,1},
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0x00400444,
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{0x00400d10,1},
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0x004004c4,
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{0x00400d50,1},
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0x00400448,
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{0x00400d90,1},
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0x004004c8,
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{0x00400d14,1},
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0x0040044c,
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{0x00400d54,1},
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0x004004cc,
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{0x00400d94,1},
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0x00400450,
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{0x00400d18,1},
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0x004004d0,
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{0x00400d58,1},
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0x00400454,
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{0x00400d98,1},
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0x004004d4,
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{0x00400d1c,1},
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0x00400458,
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{0x00400d5c,1},
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0x004004d8,
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{0x00400d9c,1},
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0x0040045c,
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{0x00400d20,1},
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0x004004dc,
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{0x00400d60,1},
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0x00400460,
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{0x00400da0,1},
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0x004004e0,
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{0x00400d24,1},
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0x00400464,
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{0x00400d64,1},
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0x004004e4,
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{0x00400da4,1},
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0x00400468,
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{0x00400d28,1},
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0x004004e8,
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{0x00400d68,1},
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0x0040046c,
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{0x00400da8,1},
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0x004004ec,
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{0x00400d2c,1},
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0x00400470,
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{0x00400d6c,1},
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0x004004f0,
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{0x00400dac,1},
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0x00400474,
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{0x00400d30,1},
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0x004004f4,
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{0x00400d70,1},
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0x00400478,
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{0x00400db0,1},
|
0x004004f8,
|
||||||
{0x00400d34,1},
|
0x0040047c,
|
||||||
{0x00400d74,1},
|
0x004004fc,
|
||||||
{0x00400db4,1},
|
0x0040053c,
|
||||||
{0x00400d38,1},
|
0x00400544,
|
||||||
{0x00400d78,1},
|
0x00400540,
|
||||||
{0x00400db8,1},
|
0x00400548,
|
||||||
{0x00400d3c,1},
|
0x00400560,
|
||||||
{0x00400d7c,1},
|
0x00400568,
|
||||||
{0x00400dbc,1},
|
0x00400564,
|
||||||
{0x00400590,1},
|
0x0040056c,
|
||||||
{0x00400594,1},
|
0x00400534,
|
||||||
{0x00400598,1},
|
0x00400538,
|
||||||
{0x0040059c,1},
|
0x00400514,
|
||||||
{0x004005a8,1},
|
0x00400518,
|
||||||
{0x004005ac,1},
|
0x0040051c,
|
||||||
{0x004005b0,1},
|
0x00400520,
|
||||||
{0x004005b4,1},
|
0x00400524,
|
||||||
{0x004005c0,1},
|
0x00400528,
|
||||||
{0x004005c4,1},
|
0x0040052c,
|
||||||
{0x004005c8,1},
|
0x00400530,
|
||||||
{0x004005cc,1},
|
0x00400d00,
|
||||||
{0x004005d0,1},
|
0x00400d40,
|
||||||
{0x004005d4,1},
|
0x00400d80,
|
||||||
{0x004005d8,1},
|
0x00400d04,
|
||||||
{0x004005dc,1},
|
0x00400d44,
|
||||||
{0x004005e0,1},
|
0x00400d84,
|
||||||
{NV04_PGRAPH_PASSTHRU_0,1},
|
0x00400d08,
|
||||||
{NV04_PGRAPH_PASSTHRU_1,1},
|
0x00400d48,
|
||||||
{NV04_PGRAPH_PASSTHRU_2,1},
|
0x00400d88,
|
||||||
{NV04_PGRAPH_DVD_COLORFMT,1},
|
0x00400d0c,
|
||||||
{NV04_PGRAPH_SCALED_FORMAT,1},
|
0x00400d4c,
|
||||||
{NV04_PGRAPH_MISC24_0,1},
|
0x00400d8c,
|
||||||
{NV04_PGRAPH_MISC24_1,1},
|
0x00400d10,
|
||||||
{NV04_PGRAPH_MISC24_2,1},
|
0x00400d50,
|
||||||
{0x00400500,1},
|
0x00400d90,
|
||||||
{0x00400504,1},
|
0x00400d14,
|
||||||
{NV04_PGRAPH_VALID1,1},
|
0x00400d54,
|
||||||
{NV04_PGRAPH_VALID2,1}
|
0x00400d94,
|
||||||
|
0x00400d18,
|
||||||
|
0x00400d58,
|
||||||
|
0x00400d98,
|
||||||
|
0x00400d1c,
|
||||||
|
0x00400d5c,
|
||||||
|
0x00400d9c,
|
||||||
|
0x00400d20,
|
||||||
|
0x00400d60,
|
||||||
|
0x00400da0,
|
||||||
|
0x00400d24,
|
||||||
|
0x00400d64,
|
||||||
|
0x00400da4,
|
||||||
|
0x00400d28,
|
||||||
|
0x00400d68,
|
||||||
|
0x00400da8,
|
||||||
|
0x00400d2c,
|
||||||
|
0x00400d6c,
|
||||||
|
0x00400dac,
|
||||||
|
0x00400d30,
|
||||||
|
0x00400d70,
|
||||||
|
0x00400db0,
|
||||||
|
0x00400d34,
|
||||||
|
0x00400d74,
|
||||||
|
0x00400db4,
|
||||||
|
0x00400d38,
|
||||||
|
0x00400d78,
|
||||||
|
0x00400db8,
|
||||||
|
0x00400d3c,
|
||||||
|
0x00400d7c,
|
||||||
|
0x00400dbc,
|
||||||
|
0x00400590,
|
||||||
|
0x00400594,
|
||||||
|
0x00400598,
|
||||||
|
0x0040059c,
|
||||||
|
0x004005a8,
|
||||||
|
0x004005ac,
|
||||||
|
0x004005b0,
|
||||||
|
0x004005b4,
|
||||||
|
0x004005c0,
|
||||||
|
0x004005c4,
|
||||||
|
0x004005c8,
|
||||||
|
0x004005cc,
|
||||||
|
0x004005d0,
|
||||||
|
0x004005d4,
|
||||||
|
0x004005d8,
|
||||||
|
0x004005dc,
|
||||||
|
0x004005e0,
|
||||||
|
NV04_PGRAPH_PASSTHRU_0,
|
||||||
|
NV04_PGRAPH_PASSTHRU_1,
|
||||||
|
NV04_PGRAPH_PASSTHRU_2,
|
||||||
|
NV04_PGRAPH_DVD_COLORFMT,
|
||||||
|
NV04_PGRAPH_SCALED_FORMAT,
|
||||||
|
NV04_PGRAPH_MISC24_0,
|
||||||
|
NV04_PGRAPH_MISC24_1,
|
||||||
|
NV04_PGRAPH_MISC24_2,
|
||||||
|
0x00400500,
|
||||||
|
0x00400504,
|
||||||
|
NV04_PGRAPH_VALID1,
|
||||||
|
NV04_PGRAPH_VALID2
|
||||||
|
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
@ -290,43 +349,35 @@ struct reg_interval
|
||||||
void nouveau_nv04_context_switch(struct drm_device *dev)
|
void nouveau_nv04_context_switch(struct drm_device *dev)
|
||||||
{
|
{
|
||||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||||
int channel, channel_old, i, j, index;
|
struct nouveau_channel *next, *last;
|
||||||
|
int chid;
|
||||||
|
|
||||||
channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
|
chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
|
||||||
channel_old = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
|
next = dev_priv->fifos[chid];
|
||||||
|
|
||||||
DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
|
chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
|
||||||
|
last = dev_priv->fifos[chid];
|
||||||
|
|
||||||
|
DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",last->id, next->id);
|
||||||
|
|
||||||
NV_WRITE(NV03_PFIFO_CACHES, 0x0);
|
NV_WRITE(NV03_PFIFO_CACHES, 0x0);
|
||||||
NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
|
NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
|
||||||
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);
|
NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);
|
||||||
NV_WRITE(NV04_PGRAPH_FIFO,0x0);
|
NV_WRITE(NV04_PGRAPH_FIFO,0x0);
|
||||||
|
|
||||||
nouveau_wait_for_idle(dev);
|
nv04_graph_save_context(last);
|
||||||
|
|
||||||
// save PGRAPH context
|
nouveau_wait_for_idle(dev);
|
||||||
index=0;
|
|
||||||
for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
|
|
||||||
for (j = 0; j<nv04_graph_ctx_regs[i].number; j++)
|
|
||||||
{
|
|
||||||
dev_priv->fifos[channel_old]->pgraph_ctx[index] = NV_READ(nv04_graph_ctx_regs[i].reg+j*4);
|
|
||||||
index++;
|
|
||||||
}
|
|
||||||
|
|
||||||
NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
|
NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
|
||||||
NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
|
NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
|
||||||
|
|
||||||
// restore PGRAPH context
|
nouveau_wait_for_idle(dev);
|
||||||
index=0;
|
|
||||||
for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
|
nv04_graph_load_context(last);
|
||||||
for (j = 0; j<nv04_graph_ctx_regs[i].number; j++)
|
|
||||||
{
|
|
||||||
NV_WRITE(nv04_graph_ctx_regs[i].reg+j*4, dev_priv->fifos[channel]->pgraph_ctx[index]);
|
|
||||||
index++;
|
|
||||||
}
|
|
||||||
|
|
||||||
NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
|
NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
|
||||||
NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24);
|
NV_WRITE(NV04_PGRAPH_CTX_USER, next->id << 24);
|
||||||
NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF);
|
NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF);
|
||||||
|
|
||||||
NV_WRITE(NV04_PGRAPH_FIFO,0x0);
|
NV_WRITE(NV04_PGRAPH_FIFO,0x0);
|
||||||
|
|
@ -356,19 +407,30 @@ void nv04_graph_destroy_context(struct nouveau_channel *chan)
|
||||||
|
|
||||||
int nv04_graph_load_context(struct nouveau_channel *chan)
|
int nv04_graph_load_context(struct nouveau_channel *chan)
|
||||||
{
|
{
|
||||||
DRM_ERROR("stub!\n");
|
struct drm_device *dev = chan->dev;
|
||||||
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
|
||||||
|
NV_WRITE(nv04_graph_ctx_regs[i], chan->pgraph_ctx[i]);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int nv04_graph_save_context(struct nouveau_channel *chan)
|
int nv04_graph_save_context(struct nouveau_channel *chan)
|
||||||
{
|
{
|
||||||
DRM_ERROR("stub!\n");
|
struct drm_device *dev = chan->dev;
|
||||||
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
|
||||||
|
chan->pgraph_ctx[i] = NV_READ(nv04_graph_ctx_regs[i]);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int nv04_graph_init(struct drm_device *dev) {
|
int nv04_graph_init(struct drm_device *dev) {
|
||||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||||
int i,sum=0;
|
|
||||||
|
|
||||||
NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
|
NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
|
||||||
~NV_PMC_ENABLE_PGRAPH);
|
~NV_PMC_ENABLE_PGRAPH);
|
||||||
|
|
@ -380,23 +442,19 @@ int nv04_graph_init(struct drm_device *dev) {
|
||||||
NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
|
NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
|
||||||
|
|
||||||
// check the context is big enough
|
// check the context is big enough
|
||||||
for ( i = 0 ; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
|
if ( sizeof(nv04_graph_ctx_regs)>sizeof(dev_priv->fifos[0]->pgraph_ctx) )
|
||||||
sum+=nv04_graph_ctx_regs[i].number;
|
|
||||||
if ( sum*4>sizeof(dev_priv->fifos[0]->pgraph_ctx) )
|
|
||||||
DRM_ERROR("pgraph_ctx too small\n");
|
DRM_ERROR("pgraph_ctx too small\n");
|
||||||
|
|
||||||
NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000);
|
|
||||||
NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
|
|
||||||
|
|
||||||
NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF);
|
NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF);
|
||||||
NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1230C000);
|
NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1231c000);
|
||||||
NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x72111101);
|
NV_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);
|
||||||
NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11D5F071);
|
NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f870);
|
||||||
NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x0004FF31);
|
NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x0004FF31);
|
||||||
NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x4004FF31 |
|
NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x4004FF31 |
|
||||||
(0x00D00000) |
|
(0x00D00000) |
|
||||||
(1<<29) |
|
(1<<29) |
|
||||||
(1<<31));
|
(1<<31));
|
||||||
|
NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xfad4ff31);
|
||||||
|
|
||||||
NV_WRITE(NV04_PGRAPH_STATE , 0xFFFFFFFF);
|
NV_WRITE(NV04_PGRAPH_STATE , 0xFFFFFFFF);
|
||||||
NV_WRITE(NV04_PGRAPH_CTX_CONTROL , 0x10010100);
|
NV_WRITE(NV04_PGRAPH_CTX_CONTROL , 0x10010100);
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue