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radeon: Always multiply pitch_bytes by nsamples, not by slice_pt 

slice_pt is tileb[0] / tile_split, which isn't directly related to the
pitch.

This caused pitch_bytes to be too large in some cases.

[0] Tile size in bytes

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
main
Michel Dänzer 2014-09-26 18:19:12 +09:00 committed by Michel Dänzer
parent 7068d987f4
commit c866dc7c00
1 changed files with 2 additions and 2 deletions
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4
radeon/radeon_surface.c
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@ -595,7 +595,7 @@ static void eg_surf_minify(struct radeon_surface *surf,
mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh;
surflevel->offset = offset;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * slice_pt;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
surflevel->slice_size = mtile_ps * mtileb * slice_pt;
surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
@ -1498,7 +1498,7 @@ static void si_surf_minify_2d(struct radeon_surface *surf,
/* macro tile per slice */
mtile_ps = (mtile_pr * surflevel->nblk_y) / yalign;
surflevel->offset = offset;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * slice_pt;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
surflevel->slice_size = mtile_ps * mtileb * slice_pt;
surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;