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When writeback isn't used, actually disable it in the hardware. 

Not doing this might waste bus bandwidth or even cause memory corruption or
system crashes on systems that check bus transfers. No such incident has been
reported though.
main
Michel Dänzer 2006-07-19 19:13:00 +02:00
parent e337eadcec
commit c91748e702
2 changed files with 7 additions and 0 deletions
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6
shared-core/radeon_cp.c
View File

@ -1258,6 +1258,12 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
dev_priv->writeback_works = 0; dev_priv->writeback_works = 0;
DRM_INFO("writeback forced off\n"); DRM_INFO("writeback forced off\n");
} }
if (!dev_priv->writeback_works) {
/* Disable writeback to avoid unnecessary bus master transfers */
RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
}
} }
/* Enable or disable PCI-E GART on the chip */ /* Enable or disable PCI-E GART on the chip */

1
shared-core/radeon_drv.h
View File

@ -679,6 +679,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
#define RADEON_CP_RB_BASE 0x0700 #define RADEON_CP_RB_BASE 0x0700
#define RADEON_CP_RB_CNTL 0x0704 #define RADEON_CP_RB_CNTL 0x0704
# define RADEON_BUF_SWAP_32BIT (2 << 16) # define RADEON_BUF_SWAP_32BIT (2 << 16)
# define RADEON_RB_NO_UPDATE (1 << 27)
#define RADEON_CP_RB_RPTR_ADDR 0x070c #define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710 #define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714 #define RADEON_CP_RB_WPTR 0x0714