tests/amdgpu: add vce mv tests support and sets
Signed-off-by: James Zhu <James.Zhu@amd.com> Acked-by: Leo Liu <leo.liu@amd.com>main
James Zhu
Leo Liu
parent
35affe89d5
commit
cb850ceb0f
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@ -315,4 +315,21 @@ static const uint32_t vce_destroy[] = {
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0x00000008,
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0x02000001,
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};
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static const uint32_t vce_mv_buffer[] = {
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0x00000038,
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0x0500000d,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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};
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#endif /*_vce_ib_h*/
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@ -37,6 +37,7 @@
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#define IB_SIZE 4096
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#define MAX_RESOURCES 16
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#define FW_53_0_03 ((53 << 24) | (0 << 16) | (03 << 8))
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struct amdgpu_vce_bo {
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amdgpu_bo_handle handle;
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@ -55,6 +56,9 @@ struct amdgpu_vce_encode {
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struct amdgpu_vce_bo cpb;
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unsigned ib_len;
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bool two_instance;
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struct amdgpu_vce_bo mvrefbuf;
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struct amdgpu_vce_bo mvb;
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unsigned mvbuf_size;
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};
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static amdgpu_device_handle device_handle;
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@ -62,6 +66,10 @@ static uint32_t major_version;
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static uint32_t minor_version;
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static uint32_t family_id;
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static uint32_t vce_harvest_config;
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static uint32_t chip_rev;
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static uint32_t chip_id;
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static uint32_t ids_flags;
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static bool is_mv_supported = true;
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static amdgpu_context_handle context_handle;
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static amdgpu_bo_handle ib_handle;
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@ -75,33 +83,58 @@ static unsigned num_resources;
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static void amdgpu_cs_vce_create(void);
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static void amdgpu_cs_vce_encode(void);
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static void amdgpu_cs_vce_encode_mv(void);
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static void amdgpu_cs_vce_destroy(void);
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CU_TestInfo vce_tests[] = {
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{ "VCE create", amdgpu_cs_vce_create },
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{ "VCE encode", amdgpu_cs_vce_encode },
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{ "VCE MV dump", amdgpu_cs_vce_encode_mv },
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{ "VCE destroy", amdgpu_cs_vce_destroy },
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CU_TEST_INFO_NULL,
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};
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CU_BOOL suite_vce_tests_enable(void)
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{
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uint32_t version, feature;
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CU_BOOL ret_mv = CU_FALSE;
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if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
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&minor_version, &device_handle))
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return CU_FALSE;
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family_id = device_handle->info.family_id;
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chip_rev = device_handle->info.chip_rev;
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chip_id = device_handle->info.chip_external_rev;
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ids_flags = device_handle->info.ids_flags;
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amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0,
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0, &version, &feature);
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if (amdgpu_device_deinitialize(device_handle))
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return CU_FALSE;
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if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
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printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
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return CU_FALSE;
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}
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if (!(chip_id == (chip_rev + 0x3C) || /* FIJI */
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chip_id == (chip_rev + 0x50) || /* Polaris 10*/
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chip_id == (chip_rev + 0x5A) || /* Polaris 11*/
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chip_id == (chip_rev + 0x64) || /* Polaris 12*/
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(family_id >= AMDGPU_FAMILY_AI && !ids_flags))) /* dGPU > Polaris */
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printf("\n\nThe ASIC NOT support VCE MV, suite disabled\n");
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else if (FW_53_0_03 > version)
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printf("\n\nThe ASIC FW version NOT support VCE MV, suite disabled\n");
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else
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ret_mv = CU_TRUE;
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if (ret_mv == CU_FALSE) {
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amdgpu_set_test_active("VCE Tests", "VCE MV dump", ret_mv);
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is_mv_supported = false;
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}
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return CU_TRUE;
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}
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@ -270,6 +303,12 @@ static void amdgpu_cs_vce_create(void)
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memcpy((ib_cpu + len), vce_create, sizeof(vce_create));
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ib_cpu[len + 8] = ALIGN(enc.width, align);
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ib_cpu[len + 9] = ALIGN(enc.width, align);
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if (is_mv_supported == true) {/* disableTwoInstance */
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if (family_id >= AMDGPU_FAMILY_AI)
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ib_cpu[len + 11] = 0x01000001;
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else
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ib_cpu[len + 11] = 0x01000201;
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}
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len += sizeof(vce_create) / 4;
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memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
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ib_cpu[len + 2] = enc.fb[0].addr >> 32;
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@ -301,6 +340,8 @@ static void amdgpu_cs_vce_config(void)
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memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo));
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len += sizeof(vce_rdo) / 4;
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memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl));
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if (is_mv_supported == true)
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ib_cpu[len + 27] = 0x00000001; /* encSliceMode */
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len += sizeof(vce_pic_ctrl) / 4;
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r = submit(len, AMDGPU_HW_IP_VCE);
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@ -521,6 +562,180 @@ static void amdgpu_cs_vce_encode(void)
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free_resource(&enc.cpb);
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}
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static void amdgpu_cs_vce_mv(struct amdgpu_vce_encode *enc)
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{
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uint64_t luma_offset, chroma_offset;
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uint64_t mv_ref_luma_offset;
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unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
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unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
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int len = 0, i, r;
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luma_offset = enc->vbuf.addr;
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chroma_offset = luma_offset + luma_size;
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mv_ref_luma_offset = enc->mvrefbuf.addr;
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memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
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len += sizeof(vce_session) / 4;
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memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
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len += sizeof(vce_taskinfo) / 4;
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memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
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ib_cpu[len + 2] = enc->bs[0].addr >> 32;
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ib_cpu[len + 3] = enc->bs[0].addr;
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len += sizeof(vce_bs_buffer) / 4;
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memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
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ib_cpu[len + 2] = enc->cpb.addr >> 32;
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ib_cpu[len + 3] = enc->cpb.addr;
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len += sizeof(vce_context_buffer) / 4;
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memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
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for (i = 0; i < 8; ++i)
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ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
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for (i = 0; i < 8; ++i)
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ib_cpu[len + 10 + i] = luma_size * 1.5;
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len += sizeof(vce_aux_buffer) / 4;
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memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
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ib_cpu[len + 2] = enc->fb[0].addr >> 32;
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ib_cpu[len + 3] = enc->fb[0].addr;
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len += sizeof(vce_feedback) / 4;
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memcpy((ib_cpu + len), vce_mv_buffer, sizeof(vce_mv_buffer));
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ib_cpu[len + 2] = mv_ref_luma_offset >> 32;
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ib_cpu[len + 3] = mv_ref_luma_offset;
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ib_cpu[len + 4] = ALIGN(enc->width, align);
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ib_cpu[len + 5] = ALIGN(enc->width, align);
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ib_cpu[len + 6] = luma_size;
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ib_cpu[len + 7] = enc->mvb.addr >> 32;
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ib_cpu[len + 8] = enc->mvb.addr;
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len += sizeof(vce_mv_buffer) / 4;
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memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
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ib_cpu[len + 2] = 0;
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ib_cpu[len + 3] = 0;
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ib_cpu[len + 4] = 0x154000;
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ib_cpu[len + 9] = luma_offset >> 32;
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ib_cpu[len + 10] = luma_offset;
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ib_cpu[len + 11] = chroma_offset >> 32;
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ib_cpu[len + 12] = chroma_offset;
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ib_cpu[len + 13] = ALIGN(enc->height, 16);;
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ib_cpu[len + 14] = ALIGN(enc->width, align);
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ib_cpu[len + 15] = ALIGN(enc->width, align);
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/* encDisableMBOffloading-encDisableTwoPipeMode-encInputPicArrayMode-encInputPicAddrMode */
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ib_cpu[len + 16] = 0x01010000;
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ib_cpu[len + 18] = 0; /* encPicType */
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ib_cpu[len + 19] = 0; /* encIdrFlag */
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ib_cpu[len + 20] = 0; /* encIdrPicId */
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ib_cpu[len + 21] = 0; /* encMGSKeyPic */
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ib_cpu[len + 22] = 0; /* encReferenceFlag */
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ib_cpu[len + 23] = 0; /* encTemporalLayerIndex */
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ib_cpu[len + 55] = 0; /* pictureStructure */
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ib_cpu[len + 56] = 0; /* encPicType -ref[0] */
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ib_cpu[len + 61] = 0; /* pictureStructure */
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ib_cpu[len + 62] = 0; /* encPicType -ref[1] */
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ib_cpu[len + 67] = 0; /* pictureStructure */
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ib_cpu[len + 68] = 0; /* encPicType -ref1 */
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ib_cpu[len + 81] = 1; /* frameNumber */
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ib_cpu[len + 82] = 2; /* pictureOrderCount */
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ib_cpu[len + 83] = 0xffffffff; /* numIPicRemainInRCGOP */
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ib_cpu[len + 84] = 0xffffffff; /* numPPicRemainInRCGOP */
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ib_cpu[len + 85] = 0xffffffff; /* numBPicRemainInRCGOP */
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ib_cpu[len + 86] = 0xffffffff; /* numIRPicRemainInRCGOP */
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ib_cpu[len + 87] = 0; /* remainedIntraRefreshPictures */
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len += sizeof(vce_encode) / 4;
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enc->ib_len = len;
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r = submit(len, AMDGPU_HW_IP_VCE);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void check_mv_result(struct amdgpu_vce_encode *enc)
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{
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uint64_t sum;
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uint32_t s = 140790;
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uint32_t *ptr, size;
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int i, j, r;
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r = amdgpu_bo_cpu_map(enc->fb[0].handle, (void **)&enc->fb[0].ptr);
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CU_ASSERT_EQUAL(r, 0);
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ptr = (uint32_t *)enc->fb[0].ptr;
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r = amdgpu_bo_cpu_unmap(enc->fb[0].handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_cpu_map(enc->mvb.handle, (void **)&enc->mvb.ptr);
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CU_ASSERT_EQUAL(r, 0);
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for (j = 0, sum = 0; j < enc->mvbuf_size; ++j)
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sum += enc->mvb.ptr[j];
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CU_ASSERT_EQUAL(sum, s);
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r = amdgpu_bo_cpu_unmap(enc->mvb.handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_cs_vce_encode_mv(void)
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{
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uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
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unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
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int i, r;
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vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
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enc.mvbuf_size = ALIGN(enc.width, 16) * ALIGN(enc.height, 16) / 8;
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cpb_size = vbuf_size * 10;
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num_resources = 0;
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alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
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resources[num_resources++] = enc.fb[0].handle;
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alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
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resources[num_resources++] = enc.bs[0].handle;
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alloc_resource(&enc.mvb, enc.mvbuf_size, AMDGPU_GEM_DOMAIN_GTT);
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resources[num_resources++] = enc.mvb.handle;
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alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
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resources[num_resources++] = enc.vbuf.handle;
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alloc_resource(&enc.mvrefbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
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resources[num_resources++] = enc.mvrefbuf.handle;
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alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
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resources[num_resources++] = enc.cpb.handle;
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resources[num_resources++] = ib_handle;
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r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
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CU_ASSERT_EQUAL(r, 0);
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memset(enc.vbuf.ptr, 0, vbuf_size);
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for (i = 0; i < enc.height; ++i) {
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memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
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enc.vbuf.ptr += ALIGN(enc.width, align);
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}
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for (i = 0; i < enc.height / 2; ++i) {
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memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width);
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enc.vbuf.ptr += ALIGN(enc.width, align);
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}
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r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_cpu_map(enc.mvrefbuf.handle, (void **)&enc.mvrefbuf.ptr);
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CU_ASSERT_EQUAL(r, 0);
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memset(enc.mvrefbuf.ptr, 0, vbuf_size);
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for (i = 0; i < enc.height; ++i) {
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memcpy(enc.mvrefbuf.ptr, (frame + (enc.height - i -1) * enc.width), enc.width);
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enc.mvrefbuf.ptr += ALIGN(enc.width, align);
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}
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for (i = 0; i < enc.height / 2; ++i) {
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memcpy(enc.mvrefbuf.ptr,
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((frame + enc.height * enc.width) + (enc.height / 2 - i -1) * enc.width), enc.width);
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enc.mvrefbuf.ptr += ALIGN(enc.width, align);
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}
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r = amdgpu_bo_cpu_unmap(enc.mvrefbuf.handle);
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CU_ASSERT_EQUAL(r, 0);
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amdgpu_cs_vce_config();
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vce_taskinfo[3] = 3;
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amdgpu_cs_vce_mv(&enc);
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check_mv_result(&enc);
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free_resource(&enc.fb[0]);
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free_resource(&enc.bs[0]);
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free_resource(&enc.vbuf);
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free_resource(&enc.cpb);
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free_resource(&enc.mvrefbuf);
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free_resource(&enc.mvb);
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}
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static void amdgpu_cs_vce_destroy(void)
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{
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int len, r;
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