Remove old i830 kernel driver.
Alan Hourihane
parent
1e77e52755
commit
cbe31d0dc7
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@ -53,22 +53,13 @@ choice
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depends on DRM && AGP && AGP_INTEL
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optional
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config DRM_I830
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tristate "i830 driver"
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help
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Choose this option if you have a system that has Intel 830M, 845G,
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852GM, 855GM or 865G integrated graphics. If M is selected, the
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module will be called i830. AGP support is required for this driver
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to work. This driver will eventually be replaced by the i915 one.
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config DRM_I915
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tristate "i915 driver"
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help
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Choose this option if you have a system that has Intel 830M, 845G,
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852GM, 855GM 865G or 915G integrated graphics. If M is selected, the
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module will be called i915. AGP support is required for this driver
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to work. This driver will eventually replace the I830 driver, when
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later release of X start to use the new DDX and DRI.
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852GM, 855GM, 865G, 915G, 915GM, 945G, 945GM and 965G integrated
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graphics. If M is selected, the module will be called i915.
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AGP support is required for this driver to work.
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endchoice
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@ -63,7 +63,7 @@ MODULE_LIST := drm.o tdfx.o r128.o radeon.o mga.o sis.o savage.o via.o \
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# Modules only for ix86 architectures
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ifneq (,$(findstring 86,$(MACHINE)))
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ARCHX86 := 1
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MODULE_LIST += i830.o i810.o i915.o
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MODULE_LIST += i810.o i915.o
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endif
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ifneq (,$(findstring sparc64,$(MACHINE)))
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@ -83,7 +83,6 @@ R128HEADERS = r128_drv.h r128_drm.h $(DRMHEADERS)
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RADEONHEADERS = radeon_drv.h radeon_drm.h r300_reg.h $(DRMHEADERS)
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MGAHEADERS = mga_drv.h mga_drm.h mga_ucode.h $(DRMHEADERS)
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I810HEADERS = i810_drv.h i810_drm.h $(DRMHEADERS)
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I830HEADERS = i830_drv.h i830_drm.h $(DRMHEADERS)
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I915HEADERS = i915_drv.h i915_drm.h $(DRMHEADERS)
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SISHEADERS= sis_drv.h sis_drm.h drm_hashtab.h drm_sman.h $(DRMHEADERS)
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SAVAGEHEADERS= savage_drv.h savage_drm.h $(DRMHEADERS)
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@ -274,7 +273,6 @@ CONFIG_DRM_MGA := n
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CONFIG_DRM_I810 := n
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CONFIG_DRM_R128 := n
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CONFIG_DRM_RADEON := n
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CONFIG_DRM_I830 := n
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CONFIG_DRM_I915 := n
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CONFIG_DRM_SIS := n
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CONFIG_DRM_FFB := n
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@ -324,9 +322,6 @@ endif
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ifneq (,$(findstring i810,$(DRM_MODULES)))
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CONFIG_DRM_I810 := m
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endif
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ifneq (,$(findstring i830,$(DRM_MODULES)))
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CONFIG_DRM_I830 := m
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endif
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ifneq (,$(findstring i915,$(DRM_MODULES)))
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CONFIG_DRM_I915 := m
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endif
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@ -339,7 +334,6 @@ $(tdfx-objs): $(TDFXHEADERS)
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$(r128-objs): $(R128HEADERS)
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$(mga-objs): $(MGAHEADERS)
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$(i810-objs): $(I810HEADERS)
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$(i830-objs): $(I830HEADERS)
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$(i915-objs): $(I915HEADERS)
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$(radeon-objs): $(RADEONHEADERS)
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$(sis-objs): $(SISHEADERS)
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@ -48,7 +48,6 @@ obj-$(CONFIG_DRM_R128) += r128.o
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obj-$(CONFIG_DRM_RADEON)+= radeon.o
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obj-$(CONFIG_DRM_MGA) += mga.o
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obj-$(CONFIG_DRM_I810) += i810.o
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obj-$(CONFIG_DRM_I830) += i830.o
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obj-$(CONFIG_DRM_I915) += i915.o
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obj-$(CONFIG_DRM_SIS) += sis.o
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obj-$(CONFIG_DRM_FFB) += ffb.o
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File diff suppressed because it is too large
Load Diff
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@ -1,342 +0,0 @@
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#ifndef _I830_DRM_H_
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#define _I830_DRM_H_
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/* WARNING: These defines must be the same as what the Xserver uses.
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* if you change them, you must change the defines in the Xserver.
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*
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* KW: Actually, you can't ever change them because doing so would
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* break backwards compatibility.
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*/
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#ifndef _I830_DEFINES_
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#define _I830_DEFINES_
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#define I830_DMA_BUF_ORDER 12
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#define I830_DMA_BUF_SZ (1<<I830_DMA_BUF_ORDER)
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#define I830_DMA_BUF_NR 256
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#define I830_NR_SAREA_CLIPRECTS 8
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/* Each region is a minimum of 64k, and there are at most 64 of them.
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*/
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#define I830_NR_TEX_REGIONS 64
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#define I830_LOG_MIN_TEX_REGION_SIZE 16
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/* KW: These aren't correct but someone set them to two and then
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* released the module. Now we can't change them as doing so would
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* break backwards compatibility.
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*/
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#define I830_TEXTURE_COUNT 2
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#define I830_TEXBLEND_COUNT I830_TEXTURE_COUNT
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#define I830_TEXBLEND_SIZE 12 /* (4 args + op) * 2 + COLOR_FACTOR */
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#define I830_UPLOAD_CTX 0x1
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#define I830_UPLOAD_BUFFERS 0x2
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#define I830_UPLOAD_CLIPRECTS 0x4
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#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */
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#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */
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#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */
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#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */
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#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */
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#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */
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#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */
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#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */
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#define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2))
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#define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2))
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#define I830_UPLOAD_TEXIMAGE_MASK 0xff00
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#define I830_UPLOAD_TEX0 0x10000
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#define I830_UPLOAD_TEX1 0x20000
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#define I830_UPLOAD_TEX2 0x40000
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#define I830_UPLOAD_TEX3 0x80000
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#define I830_UPLOAD_TEX_N(n) (0x10000 << (n))
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#define I830_UPLOAD_TEX_MASK 0xf0000
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#define I830_UPLOAD_TEXBLEND0 0x100000
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#define I830_UPLOAD_TEXBLEND1 0x200000
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#define I830_UPLOAD_TEXBLEND2 0x400000
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#define I830_UPLOAD_TEXBLEND3 0x800000
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#define I830_UPLOAD_TEXBLEND_N(n) (0x100000 << (n))
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#define I830_UPLOAD_TEXBLEND_MASK 0xf00000
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#define I830_UPLOAD_TEX_PALETTE_N(n) (0x1000000 << (n))
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#define I830_UPLOAD_TEX_PALETTE_SHARED 0x4000000
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#define I830_UPLOAD_STIPPLE 0x8000000
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/* Indices into buf.Setup where various bits of state are mirrored per
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* context and per buffer. These can be fired at the card as a unit,
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* or in a piecewise fashion as required.
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*/
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/* Destbuffer state
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* - backbuffer linear offset and pitch -- invarient in the current dri
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* - zbuffer linear offset and pitch -- also invarient
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* - drawing origin in back and depth buffers.
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*
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* Keep the depth/back buffer state here to accommodate private buffers
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* in the future.
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*/
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#define I830_DESTREG_CBUFADDR 0
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#define I830_DESTREG_DBUFADDR 1
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#define I830_DESTREG_DV0 2
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#define I830_DESTREG_DV1 3
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#define I830_DESTREG_SENABLE 4
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#define I830_DESTREG_SR0 5
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#define I830_DESTREG_SR1 6
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#define I830_DESTREG_SR2 7
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#define I830_DESTREG_DR0 8
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#define I830_DESTREG_DR1 9
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#define I830_DESTREG_DR2 10
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#define I830_DESTREG_DR3 11
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#define I830_DESTREG_DR4 12
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#define I830_DEST_SETUP_SIZE 13
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/* Context state
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*/
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#define I830_CTXREG_STATE1 0
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#define I830_CTXREG_STATE2 1
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#define I830_CTXREG_STATE3 2
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#define I830_CTXREG_STATE4 3
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#define I830_CTXREG_STATE5 4
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#define I830_CTXREG_IALPHAB 5
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#define I830_CTXREG_STENCILTST 6
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#define I830_CTXREG_ENABLES_1 7
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#define I830_CTXREG_ENABLES_2 8
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#define I830_CTXREG_AA 9
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#define I830_CTXREG_FOGCOLOR 10
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#define I830_CTXREG_BLENDCOLR0 11
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#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */
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#define I830_CTXREG_VF 13
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#define I830_CTXREG_VF2 14
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#define I830_CTXREG_MCSB0 15
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#define I830_CTXREG_MCSB1 16
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#define I830_CTX_SETUP_SIZE 17
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/* 1.3: Stipple state
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*/
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#define I830_STPREG_ST0 0
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#define I830_STPREG_ST1 1
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#define I830_STP_SETUP_SIZE 2
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/* Texture state (per tex unit)
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*/
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#define I830_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (6 dwords) */
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#define I830_TEXREG_MI1 1
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#define I830_TEXREG_MI2 2
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#define I830_TEXREG_MI3 3
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#define I830_TEXREG_MI4 4
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#define I830_TEXREG_MI5 5
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#define I830_TEXREG_MF 6 /* GFX_OP_MAP_FILTER */
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#define I830_TEXREG_MLC 7 /* GFX_OP_MAP_LOD_CTL */
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#define I830_TEXREG_MLL 8 /* GFX_OP_MAP_LOD_LIMITS */
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#define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */
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#define I830_TEX_SETUP_SIZE 10
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#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */
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#define I830_TEXREG_TM0S0 1
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#define I830_TEXREG_TM0S1 2
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#define I830_TEXREG_TM0S2 3
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#define I830_TEXREG_TM0S3 4
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#define I830_TEXREG_TM0S4 5
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#define I830_TEXREG_NOP0 6 /* noop */
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#define I830_TEXREG_NOP1 7 /* noop */
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#define I830_TEXREG_NOP2 8 /* noop */
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#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */
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#define __I830_TEX_SETUP_SIZE 10
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#define I830_FRONT 0x1
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#define I830_BACK 0x2
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#define I830_DEPTH 0x4
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#endif /* _I830_DEFINES_ */
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typedef struct _drm_i830_init {
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enum {
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I830_INIT_DMA = 0x01,
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I830_CLEANUP_DMA = 0x02
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} func;
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unsigned int mmio_offset;
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unsigned int buffers_offset;
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int sarea_priv_offset;
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unsigned int ring_start;
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unsigned int ring_end;
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unsigned int ring_size;
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unsigned int front_offset;
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unsigned int back_offset;
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unsigned int depth_offset;
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unsigned int w;
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unsigned int h;
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unsigned int pitch;
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unsigned int pitch_bits;
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unsigned int back_pitch;
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unsigned int depth_pitch;
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unsigned int cpp;
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} drm_i830_init_t;
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/* Warning: If you change the SAREA structure you must change the Xserver
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* structure as well */
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typedef struct _drm_i830_tex_region {
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unsigned char next, prev; /* indices to form a circular LRU */
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unsigned char in_use; /* owned by a client, or free? */
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int age; /* tracked by clients to update local LRU's */
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} drm_i830_tex_region_t;
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typedef struct _drm_i830_sarea {
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unsigned int ContextState[I830_CTX_SETUP_SIZE];
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unsigned int BufferState[I830_DEST_SETUP_SIZE];
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unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE];
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unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE];
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unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT];
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unsigned int Palette[2][256];
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unsigned int dirty;
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unsigned int nbox;
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drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS];
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/* Maintain an LRU of contiguous regions of texture space. If
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* you think you own a region of texture memory, and it has an
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* age different to the one you set, then you are mistaken and
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* it has been stolen by another client. If global texAge
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* hasn't changed, there is no need to walk the list.
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*
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* These regions can be used as a proxy for the fine-grained
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* texture information of other clients - by maintaining them
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* in the same lru which is used to age their own textures,
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* clients have an approximate lru for the whole of global
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* texture space, and can make informed decisions as to which
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* areas to kick out. There is no need to choose whether to
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* kick out your own texture or someone else's - simply eject
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* them all in LRU order.
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*/
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drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1];
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/* Last elt is sentinal */
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int texAge; /* last time texture was uploaded */
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int last_enqueue; /* last time a buffer was enqueued */
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int last_dispatch; /* age of the most recently dispatched buffer */
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int last_quiescent; /* */
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int ctxOwner; /* last context to upload state */
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int vertex_prim;
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int pf_enabled; /* is pageflipping allowed? */
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int pf_active;
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int pf_current_page; /* which buffer is being displayed? */
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int perf_boxes; /* performance boxes to be displayed */
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/* Here's the state for texunits 2,3:
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*/
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unsigned int TexState2[I830_TEX_SETUP_SIZE];
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unsigned int TexBlendState2[I830_TEXBLEND_SIZE];
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unsigned int TexBlendStateWordsUsed2;
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unsigned int TexState3[I830_TEX_SETUP_SIZE];
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unsigned int TexBlendState3[I830_TEXBLEND_SIZE];
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unsigned int TexBlendStateWordsUsed3;
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unsigned int StippleState[I830_STP_SETUP_SIZE];
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} drm_i830_sarea_t;
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/* Flags for perf_boxes
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*/
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#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */
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#define I830_BOX_FLIP 0x2 /* populated by kernel */
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#define I830_BOX_WAIT 0x4 /* populated by kernel & client */
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#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */
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#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */
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/* I830 specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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*/
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#define DRM_I830_INIT 0x00
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#define DRM_I830_VERTEX 0x01
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#define DRM_I830_CLEAR 0x02
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#define DRM_I830_FLUSH 0x03
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#define DRM_I830_GETAGE 0x04
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#define DRM_I830_GETBUF 0x05
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#define DRM_I830_SWAP 0x06
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#define DRM_I830_COPY 0x07
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#define DRM_I830_DOCOPY 0x08
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#define DRM_I830_FLIP 0x09
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#define DRM_I830_IRQ_EMIT 0x0a
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#define DRM_I830_IRQ_WAIT 0x0b
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#define DRM_I830_GETPARAM 0x0c
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#define DRM_I830_SETPARAM 0x0d
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#define DRM_IOCTL_I830_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_INIT, drm_i830_init_t)
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#define DRM_IOCTL_I830_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_VERTEX, drm_i830_vertex_t)
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#define DRM_IOCTL_I830_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_CLEAR, drm_i830_clear_t)
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#define DRM_IOCTL_I830_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLUSH)
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#define DRM_IOCTL_I830_GETAGE DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_GETAGE)
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#define DRM_IOCTL_I830_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETBUF, drm_i830_dma_t)
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#define DRM_IOCTL_I830_SWAP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_SWAP)
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#define DRM_IOCTL_I830_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_COPY, drm_i830_copy_t)
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#define DRM_IOCTL_I830_DOCOPY DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_DOCOPY)
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#define DRM_IOCTL_I830_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLIP)
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#define DRM_IOCTL_I830_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_EMIT, drm_i830_irq_emit_t)
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#define DRM_IOCTL_I830_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_WAIT, drm_i830_irq_wait_t)
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#define DRM_IOCTL_I830_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETPARAM, drm_i830_getparam_t)
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#define DRM_IOCTL_I830_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_SETPARAM, drm_i830_setparam_t)
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typedef struct _drm_i830_clear {
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int clear_color;
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int clear_depth;
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int flags;
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unsigned int clear_colormask;
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unsigned int clear_depthmask;
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} drm_i830_clear_t;
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/* These may be placeholders if we have more cliprects than
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* I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
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* false, indicating that the buffer will be dispatched again with a
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* new set of cliprects.
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*/
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typedef struct _drm_i830_vertex {
|
||||
int idx; /* buffer index */
|
||||
int used; /* nr bytes in use */
|
||||
int discard; /* client is finished with the buffer? */
|
||||
} drm_i830_vertex_t;
|
||||
|
||||
typedef struct _drm_i830_copy_t {
|
||||
int idx; /* buffer index */
|
||||
int used; /* nr bytes in use */
|
||||
void __user *address; /* Address to copy from */
|
||||
} drm_i830_copy_t;
|
||||
|
||||
typedef struct drm_i830_dma {
|
||||
void __user *virtual;
|
||||
int request_idx;
|
||||
int request_size;
|
||||
int granted;
|
||||
} drm_i830_dma_t;
|
||||
|
||||
/* 1.3: Userspace can request & wait on irq's:
|
||||
*/
|
||||
typedef struct drm_i830_irq_emit {
|
||||
int __user *irq_seq;
|
||||
} drm_i830_irq_emit_t;
|
||||
|
||||
typedef struct drm_i830_irq_wait {
|
||||
int irq_seq;
|
||||
} drm_i830_irq_wait_t;
|
||||
|
||||
/* 1.3: New ioctl to query kernel params:
|
||||
*/
|
||||
#define I830_PARAM_IRQ_ACTIVE 1
|
||||
|
||||
typedef struct drm_i830_getparam {
|
||||
int param;
|
||||
int __user *value;
|
||||
} drm_i830_getparam_t;
|
||||
|
||||
/* 1.3: New ioctl to set kernel params:
|
||||
*/
|
||||
#define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1
|
||||
|
||||
typedef struct drm_i830_setparam {
|
||||
int param;
|
||||
int value;
|
||||
} drm_i830_setparam_t;
|
||||
|
||||
#endif /* _I830_DRM_H_ */
|
||||
|
|
@ -1,117 +0,0 @@
|
|||
/* i830_drv.c -- I810 driver -*- linux-c -*-
|
||||
* Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com
|
||||
*
|
||||
* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
|
||||
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Rickard E. (Rik) Faith <faith@valinux.com>
|
||||
* Jeff Hartmann <jhartmann@valinux.com>
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
* Abraham vd Merwe <abraham@2d3d.co.za>
|
||||
* Keith Whitwell <keith@tungstengraphics.com>
|
||||
*/
|
||||
|
||||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
#include "i830_drm.h"
|
||||
#include "i830_drv.h"
|
||||
|
||||
#include "drm_pciids.h"
|
||||
|
||||
|
||||
static struct pci_device_id pciidlist[] = {
|
||||
i830_PCI_IDS
|
||||
};
|
||||
|
||||
static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static struct drm_driver driver = {
|
||||
.driver_features =
|
||||
DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
|
||||
DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE,
|
||||
#if USE_IRQS
|
||||
.driver_features |= DRIVER_HAVE_IRQ | DRIVER_SHARED_IRQ,
|
||||
#endif
|
||||
.dev_priv_size = sizeof(drm_i830_buf_priv_t),
|
||||
.load = i830_driver_load,
|
||||
.lastclose = i830_driver_lastclose,
|
||||
.preclose = i830_driver_preclose,
|
||||
.device_is_agp = i830_driver_device_is_agp,
|
||||
.reclaim_buffers_locked = i830_driver_reclaim_buffers_locked,
|
||||
.dma_quiescent = i830_driver_dma_quiescent,
|
||||
.get_map_ofs = drm_core_get_map_ofs,
|
||||
.get_reg_ofs = drm_core_get_reg_ofs,
|
||||
#if USE_IRQS
|
||||
.irq_preinstall = i830_driver_irq_preinstall,
|
||||
.irq_postinstall = i830_driver_irq_postinstall,
|
||||
.irq_uninstall = i830_driver_irq_uninstall,
|
||||
.irq_handler = i830_driver_irq_handler,
|
||||
#endif
|
||||
.ioctls = i830_ioctls,
|
||||
.fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = drm_open,
|
||||
.release = drm_release,
|
||||
.ioctl = drm_ioctl,
|
||||
.mmap = drm_mmap,
|
||||
.poll = drm_poll,
|
||||
.fasync = drm_fasync,
|
||||
},
|
||||
.pci_driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.id_table = pciidlist,
|
||||
.probe = probe,
|
||||
.remove = __devexit_p(drm_cleanup_pci),
|
||||
},
|
||||
|
||||
.name = DRIVER_NAME,
|
||||
.desc = DRIVER_DESC,
|
||||
.date = DRIVER_DATE,
|
||||
.major = DRIVER_MAJOR,
|
||||
.minor = DRIVER_MINOR,
|
||||
.patchlevel = DRIVER_PATCHLEVEL,
|
||||
};
|
||||
|
||||
static int probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
return drm_get_dev(pdev, ent, &driver);
|
||||
}
|
||||
|
||||
|
||||
static int __init i830_init(void)
|
||||
{
|
||||
driver.num_ioctls = i830_max_ioctl;
|
||||
return drm_init(&driver, pciidlist);
|
||||
}
|
||||
|
||||
static void __exit i830_exit(void)
|
||||
{
|
||||
drm_exit(&driver);
|
||||
}
|
||||
|
||||
module_init(i830_init);
|
||||
module_exit(i830_exit);
|
||||
|
||||
MODULE_AUTHOR(DRIVER_AUTHOR);
|
||||
MODULE_DESCRIPTION(DRIVER_DESC);
|
||||
MODULE_LICENSE("GPL and additional rights");
|
||||
|
|
@ -1,292 +0,0 @@
|
|||
/* i830_drv.h -- Private header for the I830 driver -*- linux-c -*-
|
||||
* Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
|
||||
*
|
||||
* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
|
||||
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Rickard E. (Rik) Faith <faith@valinux.com>
|
||||
* Jeff Hartmann <jhartmann@valinux.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _I830_DRV_H_
|
||||
#define _I830_DRV_H_
|
||||
|
||||
/* General customization:
|
||||
*/
|
||||
|
||||
#define DRIVER_AUTHOR "VA Linux Systems Inc."
|
||||
|
||||
#define DRIVER_NAME "i830"
|
||||
#define DRIVER_DESC "Intel 830M"
|
||||
#define DRIVER_DATE "20021108"
|
||||
|
||||
/* Interface history:
|
||||
*
|
||||
* 1.1: Original.
|
||||
* 1.2: ?
|
||||
* 1.3: New irq emit/wait ioctls.
|
||||
* New pageflip ioctl.
|
||||
* New getparam ioctl.
|
||||
* State for texunits 3&4 in sarea.
|
||||
* New (alternative) layout for texture state.
|
||||
*/
|
||||
#define DRIVER_MAJOR 1
|
||||
#define DRIVER_MINOR 3
|
||||
#define DRIVER_PATCHLEVEL 2
|
||||
|
||||
/* Driver will work either way: IRQ's save cpu time when waiting for
|
||||
* the card, but are subject to subtle interactions between bios,
|
||||
* hardware and the driver.
|
||||
*/
|
||||
/* XXX: Add vblank support? */
|
||||
#define USE_IRQS 0
|
||||
|
||||
typedef struct drm_i830_buf_priv {
|
||||
u32 *in_use;
|
||||
int my_use_idx;
|
||||
int currently_mapped;
|
||||
void __user *virtual;
|
||||
void *kernel_virtual;
|
||||
drm_local_map_t map;
|
||||
} drm_i830_buf_priv_t;
|
||||
|
||||
typedef struct _drm_i830_ring_buffer {
|
||||
int tail_mask;
|
||||
unsigned long Start;
|
||||
unsigned long End;
|
||||
unsigned long Size;
|
||||
u8 *virtual_start;
|
||||
int head;
|
||||
int tail;
|
||||
int space;
|
||||
drm_local_map_t map;
|
||||
} drm_i830_ring_buffer_t;
|
||||
|
||||
typedef struct drm_i830_private {
|
||||
drm_map_t *sarea_map;
|
||||
drm_map_t *mmio_map;
|
||||
|
||||
drm_i830_sarea_t *sarea_priv;
|
||||
drm_i830_ring_buffer_t ring;
|
||||
|
||||
void *hw_status_page;
|
||||
unsigned long counter;
|
||||
|
||||
dma_addr_t dma_status_page;
|
||||
|
||||
drm_buf_t *mmap_buffer;
|
||||
|
||||
u32 front_di1, back_di1, zi1;
|
||||
|
||||
int back_offset;
|
||||
int depth_offset;
|
||||
int front_offset;
|
||||
int w, h;
|
||||
int pitch;
|
||||
int back_pitch;
|
||||
int depth_pitch;
|
||||
unsigned int cpp;
|
||||
|
||||
int do_boxes;
|
||||
int dma_used;
|
||||
|
||||
int current_page;
|
||||
int page_flipping;
|
||||
|
||||
wait_queue_head_t irq_queue;
|
||||
atomic_t irq_received;
|
||||
atomic_t irq_emitted;
|
||||
|
||||
int use_mi_batchbuffer_start;
|
||||
|
||||
} drm_i830_private_t;
|
||||
|
||||
extern drm_ioctl_desc_t i830_ioctls[];
|
||||
extern int i830_max_ioctl;
|
||||
|
||||
/* i830_irq.c */
|
||||
extern int i830_irq_emit(struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg);
|
||||
extern int i830_irq_wait(struct inode *inode, struct file *filp,
|
||||
unsigned int cmd, unsigned long arg);
|
||||
|
||||
extern irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS);
|
||||
extern void i830_driver_irq_preinstall(drm_device_t * dev);
|
||||
extern void i830_driver_irq_postinstall(drm_device_t * dev);
|
||||
extern void i830_driver_irq_uninstall(drm_device_t * dev);
|
||||
extern int i830_driver_load(struct drm_device *, unsigned long flags);
|
||||
extern void i830_driver_preclose(drm_device_t * dev, DRMFILE filp);
|
||||
extern void i830_driver_lastclose(drm_device_t * dev);
|
||||
extern void i830_driver_reclaim_buffers_locked(drm_device_t * dev,
|
||||
struct file *filp);
|
||||
extern int i830_driver_dma_quiescent(drm_device_t * dev);
|
||||
extern int i830_driver_device_is_agp(drm_device_t * dev);
|
||||
|
||||
#define I830_READ(reg) DRM_READ32(dev_priv->mmio_map, reg)
|
||||
#define I830_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val)
|
||||
#define I830_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg)
|
||||
#define I830_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val)
|
||||
|
||||
#define I830_VERBOSE 0
|
||||
|
||||
#define RING_LOCALS unsigned int outring, ringmask, outcount; \
|
||||
volatile char *virt;
|
||||
|
||||
#define BEGIN_LP_RING(n) do { \
|
||||
if (I830_VERBOSE) \
|
||||
printk("BEGIN_LP_RING(%d) in %s\n", \
|
||||
n, __FUNCTION__); \
|
||||
if (dev_priv->ring.space < n*4) \
|
||||
i830_wait_ring(dev, n*4, __FUNCTION__); \
|
||||
outcount = 0; \
|
||||
outring = dev_priv->ring.tail; \
|
||||
ringmask = dev_priv->ring.tail_mask; \
|
||||
virt = dev_priv->ring.virtual_start; \
|
||||
} while (0)
|
||||
|
||||
#define OUT_RING(n) do { \
|
||||
if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \
|
||||
*(volatile unsigned int *)(virt + outring) = n; \
|
||||
outcount++; \
|
||||
outring += 4; \
|
||||
outring &= ringmask; \
|
||||
} while (0)
|
||||
|
||||
#define ADVANCE_LP_RING() do { \
|
||||
if (I830_VERBOSE) printk("ADVANCE_LP_RING %x\n", outring); \
|
||||
dev_priv->ring.tail = outring; \
|
||||
dev_priv->ring.space -= outcount * 4; \
|
||||
I830_WRITE(LP_RING + RING_TAIL, outring); \
|
||||
} while(0)
|
||||
|
||||
extern int i830_wait_ring(drm_device_t * dev, int n, const char *caller);
|
||||
|
||||
#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
|
||||
#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
|
||||
#define CMD_REPORT_HEAD (7<<23)
|
||||
#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
|
||||
#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
|
||||
|
||||
#define STATE3D_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16))
|
||||
#define LOAD_TEXTURE_MAP0 (1<<11)
|
||||
|
||||
#define INST_PARSER_CLIENT 0x00000000
|
||||
#define INST_OP_FLUSH 0x02000000
|
||||
#define INST_FLUSH_MAP_CACHE 0x00000001
|
||||
|
||||
#define BB1_START_ADDR_MASK (~0x7)
|
||||
#define BB1_PROTECTED (1<<0)
|
||||
#define BB1_UNPROTECTED (0<<0)
|
||||
#define BB2_END_ADDR_MASK (~0x7)
|
||||
|
||||
#define I830REG_HWSTAM 0x02098
|
||||
#define I830REG_INT_IDENTITY_R 0x020a4
|
||||
#define I830REG_INT_MASK_R 0x020a8
|
||||
#define I830REG_INT_ENABLE_R 0x020a0
|
||||
|
||||
#define I830_IRQ_RESERVED ((1<<13)|(3<<2))
|
||||
|
||||
#define LP_RING 0x2030
|
||||
#define HP_RING 0x2040
|
||||
#define RING_TAIL 0x00
|
||||
#define TAIL_ADDR 0x001FFFF8
|
||||
#define RING_HEAD 0x04
|
||||
#define HEAD_WRAP_COUNT 0xFFE00000
|
||||
#define HEAD_WRAP_ONE 0x00200000
|
||||
#define HEAD_ADDR 0x001FFFFC
|
||||
#define RING_START 0x08
|
||||
#define START_ADDR 0x0xFFFFF000
|
||||
#define RING_LEN 0x0C
|
||||
#define RING_NR_PAGES 0x001FF000
|
||||
#define RING_REPORT_MASK 0x00000006
|
||||
#define RING_REPORT_64K 0x00000002
|
||||
#define RING_REPORT_128K 0x00000004
|
||||
#define RING_NO_REPORT 0x00000000
|
||||
#define RING_VALID_MASK 0x00000001
|
||||
#define RING_VALID 0x00000001
|
||||
#define RING_INVALID 0x00000000
|
||||
|
||||
#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
|
||||
#define SC_UPDATE_SCISSOR (0x1<<1)
|
||||
#define SC_ENABLE_MASK (0x1<<0)
|
||||
#define SC_ENABLE (0x1<<0)
|
||||
|
||||
#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
|
||||
#define SCI_YMIN_MASK (0xffff<<16)
|
||||
#define SCI_XMIN_MASK (0xffff<<0)
|
||||
#define SCI_YMAX_MASK (0xffff<<16)
|
||||
#define SCI_XMAX_MASK (0xffff<<0)
|
||||
|
||||
#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
|
||||
#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
|
||||
#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
|
||||
#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
|
||||
#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
|
||||
#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
|
||||
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
|
||||
#define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24))
|
||||
|
||||
#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
|
||||
|
||||
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
|
||||
#define ASYNC_FLIP (1<<22)
|
||||
|
||||
#define CMD_3D (0x3<<29)
|
||||
#define STATE3D_CONST_BLEND_COLOR_CMD (CMD_3D|(0x1d<<24)|(0x88<<16))
|
||||
#define STATE3D_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16))
|
||||
|
||||
#define BR00_BITBLT_CLIENT 0x40000000
|
||||
#define BR00_OP_COLOR_BLT 0x10000000
|
||||
#define BR00_OP_SRC_COPY_BLT 0x10C00000
|
||||
#define BR13_SOLID_PATTERN 0x80000000
|
||||
|
||||
#define BUF_3D_ID_COLOR_BACK (0x3<<24)
|
||||
#define BUF_3D_ID_DEPTH (0x7<<24)
|
||||
#define BUF_3D_USE_FENCE (1<<23)
|
||||
#define BUF_3D_PITCH(x) (((x)/4)<<2)
|
||||
|
||||
#define CMD_OP_MAP_PALETTE_LOAD ((3<<29)|(0x1d<<24)|(0x82<<16)|255)
|
||||
#define MAP_PALETTE_NUM(x) ((x<<8) & (1<<8))
|
||||
#define MAP_PALETTE_BOTH (1<<11)
|
||||
|
||||
#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4)
|
||||
#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
|
||||
#define XY_COLOR_BLT_WRITE_RGB (1<<20)
|
||||
|
||||
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
|
||||
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
|
||||
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
|
||||
|
||||
#define MI_BATCH_BUFFER ((0x30<<23)|1)
|
||||
#define MI_BATCH_BUFFER_START (0x31<<23)
|
||||
#define MI_BATCH_BUFFER_END (0xA<<23)
|
||||
#define MI_BATCH_NON_SECURE (1)
|
||||
|
||||
#define MI_WAIT_FOR_EVENT ((0x3<<23))
|
||||
#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
|
||||
#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
|
||||
|
||||
#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
|
||||
|
||||
#endif
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
/* i830_dma.c -- DMA support for the I830 -*- linux-c -*-
|
||||
*
|
||||
* Copyright 2002 Tungsten Graphics, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Keith Whitwell <keith@tungstengraphics.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "drmP.h"
|
||||
#include "drm.h"
|
||||
#include "i830_drm.h"
|
||||
#include "i830_drv.h"
|
||||
#include <linux/interrupt.h> /* For task queue support */
|
||||
#include <linux/delay.h>
|
||||
|
||||
irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS)
|
||||
{
|
||||
drm_device_t *dev = (drm_device_t *) arg;
|
||||
drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
|
||||
u16 temp;
|
||||
|
||||
temp = I830_READ16(I830REG_INT_IDENTITY_R);
|
||||
DRM_DEBUG("%x\n", temp);
|
||||
|
||||
if (!(temp & 2))
|
||||
return IRQ_NONE;
|
||||
|
||||
I830_WRITE16(I830REG_INT_IDENTITY_R, temp);
|
||||
|
||||
atomic_inc(&dev_priv->irq_received);
|
||||
wake_up_interruptible(&dev_priv->irq_queue);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int i830_emit_irq(drm_device_t * dev)
|
||||
{
|
||||
drm_i830_private_t *dev_priv = dev->dev_private;
|
||||
RING_LOCALS;
|
||||
|
||||
DRM_DEBUG("%s\n", __FUNCTION__);
|
||||
|
||||
atomic_inc(&dev_priv->irq_emitted);
|
||||
|
||||
BEGIN_LP_RING(2);
|
||||
OUT_RING(0);
|
||||
OUT_RING(GFX_OP_USER_INTERRUPT);
|
||||
ADVANCE_LP_RING();
|
||||
|
||||
return atomic_read(&dev_priv->irq_emitted);
|
||||
}
|
||||
|
||||
static int i830_wait_irq(drm_device_t * dev, int irq_nr)
|
||||
{
|
||||
drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
|
||||
DECLARE_WAITQUEUE(entry, current);
|
||||
unsigned long end = jiffies + HZ * 3;
|
||||
int ret = 0;
|
||||
|
||||
DRM_DEBUG("%s\n", __FUNCTION__);
|
||||
|
||||
if (atomic_read(&dev_priv->irq_received) >= irq_nr)
|
||||
return 0;
|
||||
|
||||
dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
|
||||
|
||||
add_wait_queue(&dev_priv->irq_queue, &entry);
|
||||
|
||||
for (;;) {
|
||||
__set_current_state(TASK_INTERRUPTIBLE);
|
||||
if (atomic_read(&dev_priv->irq_received) >= irq_nr)
|
||||
break;
|
||||
if ((signed)(end - jiffies) <= 0) {
|
||||
DRM_ERROR("timeout iir %x imr %x ier %x hwstam %x\n",
|
||||
I830_READ16(I830REG_INT_IDENTITY_R),
|
||||
I830_READ16(I830REG_INT_MASK_R),
|
||||
I830_READ16(I830REG_INT_ENABLE_R),
|
||||
I830_READ16(I830REG_HWSTAM));
|
||||
|
||||
ret = -EBUSY; /* Lockup? Missed irq? */
|
||||
break;
|
||||
}
|
||||
schedule_timeout(HZ * 3);
|
||||
if (signal_pending(current)) {
|
||||
ret = -EINTR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
__set_current_state(TASK_RUNNING);
|
||||
remove_wait_queue(&dev_priv->irq_queue, &entry);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Needs the lock as it touches the ring.
|
||||
*/
|
||||
int i830_irq_emit(struct inode *inode, struct file *filp, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->head->dev;
|
||||
drm_i830_private_t *dev_priv = dev->dev_private;
|
||||
drm_i830_irq_emit_t emit;
|
||||
int result;
|
||||
|
||||
LOCK_TEST_WITH_RETURN(dev, filp);
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (copy_from_user
|
||||
(&emit, (drm_i830_irq_emit_t __user *) arg, sizeof(emit)))
|
||||
return -EFAULT;
|
||||
|
||||
result = i830_emit_irq(dev);
|
||||
|
||||
if (copy_to_user(emit.irq_seq, &result, sizeof(int))) {
|
||||
DRM_ERROR("copy_to_user\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Doesn't need the hardware lock.
|
||||
*/
|
||||
int i830_irq_wait(struct inode *inode, struct file *filp, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
drm_file_t *priv = filp->private_data;
|
||||
drm_device_t *dev = priv->head->dev;
|
||||
drm_i830_private_t *dev_priv = dev->dev_private;
|
||||
drm_i830_irq_wait_t irqwait;
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (copy_from_user(&irqwait, (drm_i830_irq_wait_t __user *) arg,
|
||||
sizeof(irqwait)))
|
||||
return -EFAULT;
|
||||
|
||||
return i830_wait_irq(dev, irqwait.irq_seq);
|
||||
}
|
||||
|
||||
/* drm_dma.h hooks
|
||||
*/
|
||||
void i830_driver_irq_preinstall(drm_device_t * dev)
|
||||
{
|
||||
drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
|
||||
|
||||
I830_WRITE16(I830REG_HWSTAM, 0xffff);
|
||||
I830_WRITE16(I830REG_INT_MASK_R, 0x0);
|
||||
I830_WRITE16(I830REG_INT_ENABLE_R, 0x0);
|
||||
atomic_set(&dev_priv->irq_received, 0);
|
||||
atomic_set(&dev_priv->irq_emitted, 0);
|
||||
init_waitqueue_head(&dev_priv->irq_queue);
|
||||
}
|
||||
|
||||
void i830_driver_irq_postinstall(drm_device_t * dev)
|
||||
{
|
||||
drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
|
||||
|
||||
I830_WRITE16(I830REG_INT_ENABLE_R, 0x2);
|
||||
}
|
||||
|
||||
void i830_driver_irq_uninstall(drm_device_t * dev)
|
||||
{
|
||||
drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
|
||||
if (!dev_priv)
|
||||
return;
|
||||
|
||||
I830_WRITE16(I830REG_INT_MASK_R, 0xffff);
|
||||
I830_WRITE16(I830REG_INT_ENABLE_R, 0x0);
|
||||
}
|
||||
Loading…
Reference in New Issue