tests/amdgpu: refactor dispatch/draw test
Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>main
Flora Cui
Likun Gao
parent
176e6ce6f3
commit
cc3c80c6ae
|
|
@ -282,12 +282,6 @@ CU_BOOL suite_cp_dma_tests_enable(void);
|
||||||
*/
|
*/
|
||||||
extern CU_TestInfo cp_dma_tests[];
|
extern CU_TestInfo cp_dma_tests[];
|
||||||
|
|
||||||
void amdgpu_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip_type);
|
|
||||||
void amdgpu_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip_type);
|
|
||||||
void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring,
|
|
||||||
int version, int hang);
|
|
||||||
void amdgpu_memcpy_draw_hang_slow_test(amdgpu_device_handle device_handle, uint32_t ring, int version);
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Initialize security test suite
|
* Initialize security test suite
|
||||||
*/
|
*/
|
||||||
|
|
@ -314,7 +308,12 @@ amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle
|
||||||
unsigned ip_type,
|
unsigned ip_type,
|
||||||
bool secure);
|
bool secure);
|
||||||
|
|
||||||
|
extern void amdgpu_test_dispatch_helper(amdgpu_device_handle device_handle, unsigned ip);
|
||||||
|
extern void amdgpu_test_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip);
|
||||||
|
extern void amdgpu_test_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip);
|
||||||
|
extern void amdgpu_test_draw_helper(amdgpu_device_handle device_handle);
|
||||||
|
extern void amdgpu_test_draw_hang_helper(amdgpu_device_handle device_handle);
|
||||||
|
extern void amdgpu_test_draw_hang_slow_helper(amdgpu_device_handle device_handle);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Initialize hotunplug test suite
|
* Initialize hotunplug test suite
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -511,66 +511,25 @@ static void amdgpu_illegal_mem_access()
|
||||||
|
|
||||||
static void amdgpu_dispatch_hang_gfx(void)
|
static void amdgpu_dispatch_hang_gfx(void)
|
||||||
{
|
{
|
||||||
amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX);
|
amdgpu_test_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void amdgpu_dispatch_hang_compute(void)
|
static void amdgpu_dispatch_hang_compute(void)
|
||||||
{
|
{
|
||||||
amdgpu_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
|
amdgpu_test_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void amdgpu_dispatch_hang_slow_gfx(void)
|
static void amdgpu_dispatch_hang_slow_gfx(void)
|
||||||
{
|
{
|
||||||
amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX);
|
amdgpu_test_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void amdgpu_dispatch_hang_slow_compute(void)
|
static void amdgpu_dispatch_hang_slow_compute(void)
|
||||||
{
|
{
|
||||||
amdgpu_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
|
amdgpu_test_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void amdgpu_draw_hang_gfx(void)
|
static void amdgpu_draw_hang_gfx(void)
|
||||||
{
|
{
|
||||||
int r;
|
amdgpu_test_draw_hang_helper(device_handle);
|
||||||
struct drm_amdgpu_info_hw_ip info;
|
|
||||||
uint32_t ring_id, version;
|
|
||||||
|
|
||||||
r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
|
|
||||||
CU_ASSERT_EQUAL(r, 0);
|
|
||||||
if (!info.available_rings)
|
|
||||||
printf("SKIP ... as there's no graphic ring\n");
|
|
||||||
|
|
||||||
version = info.hw_ip_version_major;
|
|
||||||
if (version != 9 && version != 10) {
|
|
||||||
printf("SKIP ... unsupported gfx version %d\n", version);
|
|
||||||
return;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
|
|
||||||
amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
|
|
||||||
amdgpu_memcpy_draw_test(device_handle, ring_id, version, 1);
|
|
||||||
amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void amdgpu_draw_hang_slow_gfx(void)
|
static void amdgpu_draw_hang_slow_gfx(void)
|
||||||
{
|
{
|
||||||
struct drm_amdgpu_info_hw_ip info;
|
amdgpu_test_draw_hang_slow_helper(device_handle);
|
||||||
uint32_t ring_id, version;
|
|
||||||
int r;
|
|
||||||
|
|
||||||
r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
|
|
||||||
CU_ASSERT_EQUAL(r, 0);
|
|
||||||
|
|
||||||
version = info.hw_ip_version_major;
|
|
||||||
if (version != 9 && version != 10) {
|
|
||||||
printf("SKIP ... unsupported gfx version %d\n", version);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
|
|
||||||
amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
|
|
||||||
amdgpu_memcpy_draw_hang_slow_test(device_handle, ring_id, version);
|
|
||||||
amdgpu_memcpy_draw_test(device_handle, ring_id, version, 0);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -25,7 +25,7 @@ if dep_cunit.found()
|
||||||
'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
|
'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
|
||||||
'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
|
'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
|
||||||
'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c',
|
'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c',
|
||||||
'hotunplug_tests.c', 'jpeg_tests.c', 'cp_dma_tests.c'
|
'hotunplug_tests.c', 'jpeg_tests.c', 'cp_dma_tests.c', 'shader_test_util.c'
|
||||||
),
|
),
|
||||||
dependencies : [dep_cunit, dep_threads, dep_atomic_ops],
|
dependencies : [dep_cunit, dep_threads, dep_atomic_ops],
|
||||||
include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
|
include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,144 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2022 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _shader_code_h_
|
||||||
|
#define _shader_code_h_
|
||||||
|
|
||||||
|
#ifndef ARRAY_SIZE
|
||||||
|
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
enum amdgpu_test_gfx_version {
|
||||||
|
AMDGPU_TEST_GFX_V9 = 0,
|
||||||
|
AMDGPU_TEST_GFX_V10,
|
||||||
|
AMDGPU_TEST_GFX_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum cs_type {
|
||||||
|
CS_BUFFERCLEAR = 0,
|
||||||
|
CS_BUFFERCOPY,
|
||||||
|
CS_HANG,
|
||||||
|
CS_HANG_SLOW,
|
||||||
|
};
|
||||||
|
|
||||||
|
enum ps_type {
|
||||||
|
PS_CONST,
|
||||||
|
PS_TEX,
|
||||||
|
PS_HANG,
|
||||||
|
PS_HANG_SLOW
|
||||||
|
};
|
||||||
|
|
||||||
|
enum vs_type {
|
||||||
|
VS_RECTPOSTEXFAST,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct reg_info {
|
||||||
|
uint32_t reg_offset; ///< Memory mapped register offset
|
||||||
|
uint32_t reg_value; ///< register value
|
||||||
|
};
|
||||||
|
|
||||||
|
#include "shader_code_hang.h"
|
||||||
|
#include "shader_code_gfx9.h"
|
||||||
|
#include "shader_code_gfx10.h"
|
||||||
|
|
||||||
|
struct shader_test_cs_shader {
|
||||||
|
const uint32_t *shader;
|
||||||
|
uint32_t shader_size;
|
||||||
|
const struct reg_info *sh_reg;
|
||||||
|
uint32_t num_sh_reg;
|
||||||
|
const struct reg_info *context_reg;
|
||||||
|
uint32_t num_context_reg;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct shader_test_ps_shader {
|
||||||
|
const uint32_t *shader;
|
||||||
|
unsigned shader_size;
|
||||||
|
const uint32_t patchinfo_code_size;
|
||||||
|
const uint32_t *patchinfo_code;
|
||||||
|
const uint32_t *patchinfo_code_offset;
|
||||||
|
const struct reg_info *sh_reg;
|
||||||
|
const uint32_t num_sh_reg;
|
||||||
|
const struct reg_info *context_reg;
|
||||||
|
const uint32_t num_context_reg;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct shader_test_vs_shader {
|
||||||
|
const uint32_t *shader;
|
||||||
|
uint32_t shader_size;
|
||||||
|
const struct reg_info *sh_reg;
|
||||||
|
uint32_t num_sh_reg;
|
||||||
|
const struct reg_info *context_reg;
|
||||||
|
uint32_t num_context_reg;
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2] = {
|
||||||
|
// gfx9, cs_bufferclear
|
||||||
|
{{bufferclear_cs_shader_gfx9, sizeof(bufferclear_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
|
||||||
|
// gfx9, cs_buffercopy
|
||||||
|
{buffercopy_cs_shader_gfx9, sizeof(buffercopy_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
|
||||||
|
// gfx10, cs_bufferclear
|
||||||
|
{{bufferclear_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
|
||||||
|
// gfx10, cs_buffercopy
|
||||||
|
{buffercopy_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SHADER_PS_INFO(_ps, _n) \
|
||||||
|
{ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \
|
||||||
|
ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
|
||||||
|
ps_##_ps##_shader_patchinfo_code_gfx##_n, \
|
||||||
|
ps_##_ps##_shader_patchinfo_offset_gfx##_n, \
|
||||||
|
ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \
|
||||||
|
ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n}
|
||||||
|
static const struct shader_test_ps_shader shader_test_ps[AMDGPU_TEST_GFX_MAX][2] = {
|
||||||
|
{SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)},
|
||||||
|
{SHADER_PS_INFO(const, 10), SHADER_PS_INFO(tex, 10)},
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SHADER_VS_INFO(_vs, _n) \
|
||||||
|
{vs_##_vs##_shader_gfx##_n, sizeof(vs_##_vs##_shader_gfx##_n), \
|
||||||
|
vs_##_vs##_sh_registers_gfx##_n, vs_##_vs##_num_sh_registers_gfx##_n, \
|
||||||
|
vs_##_vs##_context_registers_gfx##_n, vs_##_vs##_num_context_registers_gfx##_n}
|
||||||
|
static const struct shader_test_vs_shader shader_test_vs[AMDGPU_TEST_GFX_MAX][1] = {
|
||||||
|
{SHADER_VS_INFO(RectPosTexFast, 9)},
|
||||||
|
{SHADER_VS_INFO(RectPosTexFast, 10)},
|
||||||
|
};
|
||||||
|
|
||||||
|
struct shader_test_gfx_info {
|
||||||
|
const uint32_t *preamble_cache;
|
||||||
|
uint32_t size_preamble_cache;
|
||||||
|
const uint32_t *cached_cmd;
|
||||||
|
uint32_t size_cached_cmd;
|
||||||
|
uint32_t sh_reg_base;
|
||||||
|
uint32_t context_reg_base;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define SHADER_TEST_GFX_INFO(_n) \
|
||||||
|
preamblecache_gfx##_n, sizeof(preamblecache_gfx##_n), \
|
||||||
|
cached_cmd_gfx##_n, sizeof(cached_cmd_gfx##_n), \
|
||||||
|
sh_reg_base_gfx##_n, context_reg_base_gfx##_n
|
||||||
|
|
||||||
|
static struct shader_test_gfx_info shader_test_gfx_info[AMDGPU_TEST_GFX_MAX] = {
|
||||||
|
{SHADER_TEST_GFX_INFO(9),},
|
||||||
|
{SHADER_TEST_GFX_INFO(10),},
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,202 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2022 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _shader_code_gfx10_h_
|
||||||
|
#define _shader_code_gfx10_h_
|
||||||
|
|
||||||
|
static const uint32_t bufferclear_cs_shader_gfx10[] = {
|
||||||
|
0xD7460004, 0x04010C08, 0x7E000204, 0x7E020205,
|
||||||
|
0x7E040206, 0x7E060207, 0xE01C2000, 0x80000004,
|
||||||
|
0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t buffercopy_cs_shader_gfx10[] = {
|
||||||
|
0xD7460001, 0x04010C08, 0xE00C2000, 0x80000201,
|
||||||
|
0xBF8C3F70, 0xE01C2000, 0x80010201, 0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_shader_gfx10[] = {
|
||||||
|
0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
|
||||||
|
0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000,
|
||||||
|
0xF8001C0F, 0x00000100, 0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6;
|
||||||
|
|
||||||
|
static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = {
|
||||||
|
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000000 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000100 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000300 },
|
||||||
|
{ 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xD7690000, 0x00020300, 0xD7690001, 0x00020702, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xD7680000, 0x00020300, 0xD7680001, 0x00020702, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xD76A0000, 0x00020300, 0xD76A0001, 0x00020702, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xD76B0000, 0x00020300, 0xD76B0001, 0x00020702, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100 }
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = {
|
||||||
|
0x00000004
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_num_sh_registers_gfx10 = 2;
|
||||||
|
|
||||||
|
static const struct reg_info ps_const_sh_registers_gfx10[] = {
|
||||||
|
{0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 },
|
||||||
|
{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct reg_info ps_const_context_registers_gfx10[] =
|
||||||
|
{
|
||||||
|
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
|
||||||
|
{0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 },
|
||||||
|
{0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
|
||||||
|
{0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
|
||||||
|
{0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
|
||||||
|
{0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
|
||||||
|
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_num_context_registers_gfx10 = 7;
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_shader_gfx10[] = {
|
||||||
|
0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000,
|
||||||
|
0xC80C0100, 0xC8090001, 0xC80D0101, 0xF0800F0A,
|
||||||
|
0x00400402, 0x00000003, 0xBEFE040E, 0xBF8C0F70,
|
||||||
|
0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000,
|
||||||
|
0xF8001C0F, 0x00000100, 0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = {
|
||||||
|
0x0000000C
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6;
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = {
|
||||||
|
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000004 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000504 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000704 },
|
||||||
|
{ 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xD7690000, 0x00020B04, 0xD7690001, 0x00020F06, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xD7680000, 0x00020B04, 0xD7680001, 0x00020F06, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xD76A0000, 0x00020B04, 0xD76A0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xD76B0000, 0x00020B04, 0xD76B0001, 0x00020F06, 0xF8001C0F, 0x00000100 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x07060504 }
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct reg_info ps_tex_sh_registers_gfx10[] =
|
||||||
|
{
|
||||||
|
{0x2C0A, 0xc0081}, //0x020C0080 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0080 },
|
||||||
|
{0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_num_sh_registers_gfx10 = 2;
|
||||||
|
|
||||||
|
// Holds Context Register Information
|
||||||
|
static const struct reg_info ps_tex_context_registers_gfx10[] =
|
||||||
|
{
|
||||||
|
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
|
||||||
|
{0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 },
|
||||||
|
{0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
|
||||||
|
{0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
|
||||||
|
{0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
|
||||||
|
{0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
|
||||||
|
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_num_context_registers_gfx10 = 7;
|
||||||
|
|
||||||
|
static const uint32_t vs_RectPosTexFast_shader_gfx10[] = {
|
||||||
|
0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206,
|
||||||
|
0x7C040080, 0x060000F3, 0xD5010001, 0x01AA0200,
|
||||||
|
0x7E060203, 0xD5010002, 0x01AA0404, 0x7E080207,
|
||||||
|
0x7C040080, 0xD5010000, 0x01A80101, 0xD5010001,
|
||||||
|
0x01AA0601, 0x7E060208, 0x7E0A02F2, 0xD5010002,
|
||||||
|
0x01A80902, 0xD5010004, 0x01AA0805, 0x7E0C0209,
|
||||||
|
0xF80008CF, 0x05030100, 0xF800020F, 0x05060402,
|
||||||
|
0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct reg_info vs_RectPosTexFast_sh_registers_gfx10[] =
|
||||||
|
{
|
||||||
|
{0x2C4A, 0x080C0041 }, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x080C0041 },
|
||||||
|
{0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx10 = 2;
|
||||||
|
|
||||||
|
// Holds Context Register Information
|
||||||
|
static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] =
|
||||||
|
{
|
||||||
|
{0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
|
||||||
|
{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t vs_RectPosTexFast_num_context_registers_gfx10 = 2;
|
||||||
|
|
||||||
|
static const uint32_t preamblecache_gfx10[] = {
|
||||||
|
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
|
||||||
|
0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
|
||||||
|
0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
|
||||||
|
0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
|
||||||
|
0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
|
||||||
|
0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
|
||||||
|
0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
|
||||||
|
0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
|
||||||
|
0xc0046900, 0x310, 0, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0xe, 0x20,
|
||||||
|
0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
|
||||||
|
0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x6, 0x0,
|
||||||
|
0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||||
|
0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||||
|
0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
|
||||||
|
0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
|
||||||
|
0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
|
||||||
|
0xc0016900, 0x2db, 0, 0xc0016900, 0x1d4, 0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, 0xc0016900, 0xe, 0x2,
|
||||||
|
0xc0016900, 0x206, 0x300, 0xc0016900, 0x212, 0x200, 0xc0017900, 0x7b, 0x20, 0xc0017a00, 0x20000243, 0x0,
|
||||||
|
0xc0017900, 0x249, 0, 0xc0017900, 0x24a, 0, 0xc0017900, 0x24b, 0, 0xc0017900, 0x259, 0xffffffff,
|
||||||
|
0xc0017900, 0x25f, 0, 0xc0017900, 0x260, 0, 0xc0017900, 0x262, 0,
|
||||||
|
0xc0017600, 0x45, 0x0, 0xc0017600, 0x6, 0x0,
|
||||||
|
0xc0067600, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||||
|
0xc0067600, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t cached_cmd_gfx10[] = {
|
||||||
|
0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
|
||||||
|
0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
|
||||||
|
0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
|
||||||
|
0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x18,
|
||||||
|
0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
|
||||||
|
0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
|
||||||
|
0xc0026900, 0x292, 0x20, 0x6020000,
|
||||||
|
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t sh_reg_base_gfx10 = 0x2C00;
|
||||||
|
static const uint32_t context_reg_base_gfx10 = 0xA000;
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,204 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2022 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _shader_code_gfx9_h_
|
||||||
|
#define _shader_code_gfx9_h_
|
||||||
|
|
||||||
|
static const uint32_t bufferclear_cs_shader_gfx9[] = {
|
||||||
|
0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
|
||||||
|
0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206,
|
||||||
|
0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000,
|
||||||
|
0xbf810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct reg_info bufferclear_cs_shader_registers_gfx9[] = {
|
||||||
|
{0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
|
||||||
|
{0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 },
|
||||||
|
{0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
|
||||||
|
{0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
|
||||||
|
{0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t buffercopy_cs_shader_gfx9[] = {
|
||||||
|
0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08,
|
||||||
|
0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70,
|
||||||
|
0xe01c2000, 0x80010200, 0xbf810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_shader_gfx9[] = {
|
||||||
|
0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
|
||||||
|
0xD2960000, 0x00020300, 0xD2960001, 0x00020702,
|
||||||
|
0xC4001C0F, 0x00000100, 0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
|
||||||
|
|
||||||
|
static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
|
||||||
|
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000000 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000100 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000300 },
|
||||||
|
{ 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xD2950000, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xD2940000, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xD2970000, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xD2980000, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x03020100 }
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
|
||||||
|
0x00000004
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_num_sh_registers_gfx9 = 2;
|
||||||
|
|
||||||
|
static const struct reg_info ps_const_sh_registers_gfx9[] = {
|
||||||
|
{0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
|
||||||
|
{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_const_num_context_registers_gfx9 = 7;
|
||||||
|
|
||||||
|
static const struct reg_info ps_const_context_registers_gfx9[] = {
|
||||||
|
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
|
||||||
|
{0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 },
|
||||||
|
{0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
|
||||||
|
{0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
|
||||||
|
{0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
|
||||||
|
{0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
|
||||||
|
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_shader_gfx9[] = {
|
||||||
|
0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000,
|
||||||
|
0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00,
|
||||||
|
0x00400206, 0xBEFE010E, 0xBF8C0F70, 0xD2960000,
|
||||||
|
0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F,
|
||||||
|
0x00000100, 0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
|
||||||
|
0x0000000B
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6;
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
|
||||||
|
{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000002 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000302 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000502 },
|
||||||
|
{ 0xD2960000, 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xD2950000, 0x00020702, 0xD2950001, 0x00020B04, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xD2940000, 0x00020702, 0xD2940001, 0x00020B04, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xD2970000, 0x00020702, 0xD2970001, 0x00020B04, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xD2980000, 0x00020702, 0xD2980001, 0x00020B04, 0xC4001C0F, 0x00000100 },
|
||||||
|
{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x05040302 }
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_num_sh_registers_gfx9 = 2;
|
||||||
|
static const struct reg_info ps_tex_sh_registers_gfx9[] = {
|
||||||
|
{0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
|
||||||
|
{0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t ps_tex_num_context_registers_gfx9 = 7;
|
||||||
|
|
||||||
|
static const struct reg_info ps_tex_context_registers_gfx9[] = {
|
||||||
|
{0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
|
||||||
|
{0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 },
|
||||||
|
{0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
|
||||||
|
{0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
|
||||||
|
{0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
|
||||||
|
{0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
|
||||||
|
{0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
|
||||||
|
0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100,
|
||||||
|
0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206,
|
||||||
|
0x7E080204, 0xD1000001, 0x002A0302, 0x7C840080,
|
||||||
|
0x7E000200, 0x7E040203, 0x7E0A0201, 0xD1000003,
|
||||||
|
0x002A0704, 0x7E0C0207, 0x7E0E0205, 0x00000101,
|
||||||
|
0x00020505, 0x7E040208, 0x7E0A02F2, 0x00060903,
|
||||||
|
0x00080D07, 0x7E0C0209, 0xC40008CF, 0x05020100,
|
||||||
|
0xC400020F, 0x05060403, 0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct reg_info vs_RectPosTexFast_sh_registers_gfx9[] =
|
||||||
|
{
|
||||||
|
{0x2C4A, 0x000C0081}, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x000C0081 },
|
||||||
|
{0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 }
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx9 = 2;
|
||||||
|
|
||||||
|
// Holds Context Register Information
|
||||||
|
static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] =
|
||||||
|
{
|
||||||
|
{0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
|
||||||
|
{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t vs_RectPosTexFast_num_context_registers_gfx9 = 2;
|
||||||
|
|
||||||
|
static const uint32_t preamblecache_gfx9[] = {
|
||||||
|
0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
|
||||||
|
0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
|
||||||
|
0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
|
||||||
|
0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
|
||||||
|
0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
|
||||||
|
0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
|
||||||
|
0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
|
||||||
|
0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
|
||||||
|
0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20,
|
||||||
|
0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
|
||||||
|
0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
|
||||||
|
0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||||
|
0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
|
||||||
|
0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
|
||||||
|
0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
|
||||||
|
0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0,
|
||||||
|
0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
|
||||||
|
0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0,
|
||||||
|
0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0,
|
||||||
|
0xc0017900, 0x24b, 0x0
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t cached_cmd_gfx9[] = {
|
||||||
|
0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
|
||||||
|
0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
|
||||||
|
0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
|
||||||
|
0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x12,
|
||||||
|
0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
|
||||||
|
0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
|
||||||
|
0xc0026900, 0x292, 0x20, 0x60201b8,
|
||||||
|
0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
|
||||||
|
};
|
||||||
|
|
||||||
|
static const uint32_t sh_reg_base_gfx9 = 0x2C00;
|
||||||
|
static const uint32_t context_reg_base_gfx9 = 0xA000;
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,104 @@
|
||||||
|
/*
|
||||||
|
* Copyright 2022 Advanced Micro Devices, Inc.
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
* copy of this software and associated documentation files (the "Software"),
|
||||||
|
* to deal in the Software without restriction, including without limitation
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||||
|
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _shader_code_hang_h_
|
||||||
|
#define _shader_code_hang_h_
|
||||||
|
|
||||||
|
static const unsigned int memcpy_shader_hang[] = {
|
||||||
|
0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100,
|
||||||
|
0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001,
|
||||||
|
0xC80D0101, 0xBF8C007F, 0xF0800F00, 0x00010002,
|
||||||
|
0xBEFE040C, 0xBF8C0F70, 0xBF800000, 0xBF800000,
|
||||||
|
0xF800180F, 0x03020100, 0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
struct shader_test_shader_bin {
|
||||||
|
const uint32_t *shader;
|
||||||
|
uint32_t header_length;
|
||||||
|
uint32_t body_length;
|
||||||
|
uint32_t foot_length;
|
||||||
|
};
|
||||||
|
|
||||||
|
static const unsigned int memcpy_cs_hang_slow_ai_codes[] = {
|
||||||
|
0xd1fd0000, 0x04010c08, 0xe00c2000, 0x80000100,
|
||||||
|
0xbf8c0f70, 0xe01c2000, 0x80010100, 0xbf810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct shader_test_shader_bin memcpy_cs_hang_slow_ai = {
|
||||||
|
memcpy_cs_hang_slow_ai_codes, 4, 3, 1
|
||||||
|
};
|
||||||
|
|
||||||
|
static const unsigned int memcpy_cs_hang_slow_rv_codes[] = {
|
||||||
|
0x8e00860c, 0x32000000, 0xe00c2000, 0x80010100,
|
||||||
|
0xbf8c0f70, 0xe01c2000, 0x80020100, 0xbf810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct shader_test_shader_bin memcpy_cs_hang_slow_rv = {
|
||||||
|
memcpy_cs_hang_slow_rv_codes, 4, 3, 1
|
||||||
|
};
|
||||||
|
|
||||||
|
static const unsigned int memcpy_cs_hang_slow_nv_codes[] = {
|
||||||
|
0xd7460000, 0x04010c08, 0xe00c2000, 0x80000100,
|
||||||
|
0xbf8c0f70, 0xe01ca000, 0x80010100, 0xbf810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct shader_test_shader_bin memcpy_cs_hang_slow_nv = {
|
||||||
|
memcpy_cs_hang_slow_nv_codes, 4, 3, 1
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
static const unsigned int memcpy_ps_hang_slow_ai_codes[] = {
|
||||||
|
0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000,
|
||||||
|
0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00,
|
||||||
|
0x00400002, 0xbefe010e, 0xbf8c0f70, 0xbf800000,
|
||||||
|
0xbf800000, 0xbf800000, 0xbf800000, 0xc400180f,
|
||||||
|
0x03020100, 0xbf810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct shader_test_shader_bin memcpy_ps_hang_slow_ai = {
|
||||||
|
memcpy_ps_hang_slow_ai_codes, 7, 2, 9
|
||||||
|
};
|
||||||
|
|
||||||
|
static const unsigned int memcpy_ps_hang_slow_navi10_codes[] = {
|
||||||
|
0xBEFC030C,0xBE8E047E,0xBEFE0A7E,0xC8080000,
|
||||||
|
0xC80C0100,0xC8090001,0xC80D0101,0xF0800F0A,
|
||||||
|
0x00400402,0x00000003,0xBEFE040E,0xBF8C0F70,
|
||||||
|
0xBF800000,0xBF800000,0xBF800000,0xBF800000,
|
||||||
|
0xF800180F,0x07060504,0xBF810000
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct shader_test_shader_bin memcpy_ps_hang_slow_navi10 = {
|
||||||
|
memcpy_ps_hang_slow_navi10_codes, 7, 3, 9
|
||||||
|
};
|
||||||
|
|
||||||
|
static const unsigned int memcpy_ps_hang_slow_navi21_codes[] = {
|
||||||
|
0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000, 0xC8000100, 0xC8090001, 0xC8010101, 0x87FE0E7E, // header
|
||||||
|
0xF0800F0A, 0x00400002, 0x00000000, // body - image_sample instruction
|
||||||
|
0xBFA3FFE3, 0xBEFE040E, 0xBF8C3F70, 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100, 0xBF810000 // footer
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct shader_test_shader_bin memcpy_ps_hang_slow_navi21 = {
|
||||||
|
memcpy_ps_hang_slow_navi21_codes, 8, 3, 10
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue