headers: drm: Sync with drm-next
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - b10733527bfd864605c33ab2e9a886eec317ec39
The changes were as follows (shortlog from
14d2bd53a47a7e1cb3e03d00a6b952734cf90f3f):
core: (drm_mode.h)
Alexander A. Klimov (1):
drm: Replace HTTP links with HTTPS ones
Noralf Trønnes (1):
drm: Add SPI connector type
Oleg Vasilev (1):
drm: report dp downstream port type as a subconnector property
Simon Ser (1):
drm: document that blobs are ref'counted
Uma Shankar (3):
drm: Add HDR source metadata property
drm: Fixed doc warnings in drm uapi header
drm: Fix docbook warnings in hdr metadata helper structures
core: (drm_fourcc.h)
Adam Jackson (1):
drm/fourcc: Fix undefined left shift in DRM_FORMAT_BIG_ENDIAN macros
Bas Nieuwenhuizen (2):
drm/fourcc: Add AMD DRM modifiers.
drm/fourcc: Fix modifier field mask for AMD modifiers.
Ben Davis (2):
drm: drm_fourcc: add NV15, Q410, Q401 YUV formats
drm: drm_fourcc: Add uncompressed AFBC modifier
Brian Starkey (1):
drm: drm_fourcc: Add generic alias for 16_16_TILE modifier
Dave Airlie (1):
Merge tag 'amd-drm-next-5.11-2020-11-05' of git://people.freedesktop.org/~agd5f/linux into drm-next
Dhinakaran Pandiyan (2):
drm/framebuffer: Format modifier for Intel Gen-12 render compression
drm/framebuffer: Format modifier for Intel Gen-12 media compression
James Jones (1):
drm: Generalized NV Block Linear DRM format mod
Maarten Lankhorst (1):
Backmerge remote-tracking branch 'drm/drm-next' into drm-misc-next
Matteo Franchin (1):
drm/fourcc: Add AXBXGXRX106106106106 format
Mika Kahola (1):
uapi/drm/drm_fourcc.h: Note on platform specificity for format modifiers
Neil Armstrong (2):
drm/fourcc: Add modifier definitions for describing Amlogic Video Framebuffer Compression
drm/fourcc: fix Amlogic Video Framebuffer Compression macro
Raymond Smith (1):
drm/fourcc: Add Arm 16x16 block modifier
Simon Ser (4):
drm/fourcc: document modifier uniqueness requirements
drm: deprecate DRM_FORMAT_MOD_NONE
drm/fourcc: add table describing AMD modifiers bit layout
drm/fourcc: fix AMD modifiers PACKERS field doc
Signed-off-by: Antonin Décimo <antonin.decimo@gmail.com>
main
Antonin Décimo
Simon Ser
parent
4f0fe66369
commit
cdd14e92e9
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@ -58,6 +58,30 @@ extern "C" {
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* may preserve meaning - such as number of planes - from the fourcc code,
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* whereas others may not.
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*
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* Modifiers must uniquely encode buffer layout. In other words, a buffer must
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* match only a single modifier. A modifier must not be a subset of layouts of
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* another modifier. For instance, it's incorrect to encode pitch alignment in
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* a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
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* aligned modifier. That said, modifiers can have implicit minimal
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* requirements.
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*
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* For modifiers where the combination of fourcc code and modifier can alias,
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* a canonical pair needs to be defined and used by all drivers. Preferred
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* combinations are also encouraged where all combinations might lead to
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* confusion and unnecessarily reduced interoperability. An example for the
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* latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
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*
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* There are two kinds of modifier users:
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*
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* - Kernel and user-space drivers: for drivers it's important that modifiers
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* don't alias, otherwise two drivers might support the same format but use
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* different aliases, preventing them from sharing buffers in an efficient
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* format.
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* - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
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* see modifiers as opaque tokens they can check for equality and intersect.
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* These users musn't need to know to reason about the modifier value
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* (i.e. they are not expected to extract information out of the modifier).
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*
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* Vendors should document their modifier usage in as much detail as
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* possible, to ensure maximum compatibility across devices, drivers and
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* applications.
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@ -69,7 +93,7 @@ extern "C" {
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#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
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((__u32)(c) << 16) | ((__u32)(d) << 24))
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#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
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#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
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/* Reserve 0 for the invalid format specifier */
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#define DRM_FORMAT_INVALID 0
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@ -155,6 +179,12 @@ extern "C" {
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#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
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#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
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/*
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* RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
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* of unused padding per component:
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*/
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#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
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/* packed YCbCr */
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#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
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#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
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@ -236,6 +266,12 @@ extern "C" {
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#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
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#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
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#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
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/*
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* 2 plane YCbCr
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* index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
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* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
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*/
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#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
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/*
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* 2 plane YCbCr MSB aligned
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@ -265,6 +301,22 @@ extern "C" {
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*/
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#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
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/* 3 plane non-subsampled (444) YCbCr
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* 16 bits per component, but only 10 bits are used and 6 bits are padded
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* index 0: Y plane, [15:0] Y:x [10:6] little endian
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* index 1: Cb plane, [15:0] Cb:x [10:6] little endian
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* index 2: Cr plane, [15:0] Cr:x [10:6] little endian
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*/
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#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
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/* 3 plane non-subsampled (444) YCrCb
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* 16 bits per component, but only 10 bits are used and 6 bits are padded
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* index 0: Y plane, [15:0] Y:x [10:6] little endian
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* index 1: Cr plane, [15:0] Cr:x [10:6] little endian
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* index 2: Cb plane, [15:0] Cb:x [10:6] little endian
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*/
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#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
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/*
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* 3 plane YCbCr
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* index 0: Y plane, [7:0] Y
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@ -298,7 +350,6 @@ extern "C" {
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*/
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/* Vendor Ids: */
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#define DRM_FORMAT_MOD_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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@ -309,6 +360,7 @@ extern "C" {
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#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
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#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
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#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
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#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
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/* add more to the end as needed */
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@ -323,8 +375,33 @@ extern "C" {
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* When adding a new token please document the layout with a code comment,
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* similar to the fourcc codes above. drm_fourcc.h is considered the
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* authoritative source for all of these.
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*
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* Generic modifier names:
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*
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* DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
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* for layouts which are common across multiple vendors. To preserve
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* compatibility, in cases where a vendor-specific definition already exists and
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* a generic name for it is desired, the common name is a purely symbolic alias
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* and must use the same numerical value as the original definition.
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*
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* Note that generic names should only be used for modifiers which describe
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* generic layouts (such as pixel re-ordering), which may have
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* independently-developed support across multiple vendors.
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*
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* In future cases where a generic layout is identified before merging with a
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* vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
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* 'NONE' could be considered. This should only be for obvious, exceptional
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* cases to avoid polluting the 'GENERIC' namespace with modifiers which only
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* apply to a single vendor.
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*
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* Generic names should not be used for cases where multiple hardware vendors
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* have implementations of the same standardised compression scheme (such as
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* AFBC). In those cases, all implementations should use the same format
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* modifier(s), reflecting the vendor of the standard.
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*/
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#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
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/*
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* Invalid Modifier
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*
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@ -344,6 +421,16 @@ extern "C" {
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*/
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#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
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/*
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* Deprecated: use DRM_FORMAT_MOD_LINEAR instead
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*
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* The "none" format modifier doesn't actually mean that the modifier is
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* implicit, instead it means that the layout is linear. Whether modifiers are
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* used is out-of-band information carried in an API-specific way (e.g. in a
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* flag for drm_mode_fb_cmd2).
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*/
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#define DRM_FORMAT_MOD_NONE 0
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/* Intel framebuffer modifiers */
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/*
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@ -354,9 +441,12 @@ extern "C" {
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* a platform-dependent stride. On top of that the memory can apply
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* platform-depending swizzling of some higher address bits into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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* Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
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* On earlier platforms the is highly platforms specific and not useful for
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* cross-driver sharing. It exists since on a given platform it does uniquely
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* identify the layout in a simple way for i915-specific userspace, which
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* facilitated conversion of userspace to modifiers. Additionally the exact
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* format on some really old platforms is not known.
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*/
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#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
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@ -369,9 +459,12 @@ extern "C" {
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* memory can apply platform-depending swizzling of some higher address bits
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* into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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* Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
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* On earlier platforms the is highly platforms specific and not useful for
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* cross-driver sharing. It exists since on a given platform it does uniquely
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* identify the layout in a simple way for i915-specific userspace, which
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* facilitated conversion of userspace to modifiers. Additionally the exact
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* format on some really old platforms is not known.
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*/
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#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
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@ -410,6 +503,30 @@ extern "C" {
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#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
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#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
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/*
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* Intel color control surfaces (CCS) for Gen-12 render compression.
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*
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* The main surface is Y-tiled and at plane index 0, the CCS is linear and
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* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
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* main surface. In other words, 4 bits in CCS map to a main surface cache
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* line pair. The main surface pitch is required to be a multiple of four
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* Y-tile widths.
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
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/*
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* Intel color control surfaces (CCS) for Gen-12 media compression
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*
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* The main surface is Y-tiled and at plane index 0, the CCS is linear and
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* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
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* main surface. In other words, 4 bits in CCS map to a main surface cache
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* line pair. The main surface pitch is required to be a multiple of four
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* Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
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* Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
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* planes 2 and 3 for the respective CCS.
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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@ -497,7 +614,113 @@ extern "C" {
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#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
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/*
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* 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
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* Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
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* and Tegra GPUs starting with Tegra K1.
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*
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* Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
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* based on the architecture generation. GOBs themselves are then arranged in
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* 3D blocks, with the block dimensions (in terms of GOBs) always being a power
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* of two, and hence expressible as their log2 equivalent (E.g., "2" represents
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* a block depth or height of "4").
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*
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* Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
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* in full detail.
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*
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* Macro
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* Bits Param Description
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* ---- ----- -----------------------------------------------------------------
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*
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* 3:0 h log2(height) of each block, in GOBs. Placed here for
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* compatibility with the existing
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* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
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*
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* 4:4 - Must be 1, to indicate block-linear layout. Necessary for
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* compatibility with the existing
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* DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
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*
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* 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
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* size). Must be zero.
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*
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* Note there is no log2(width) parameter. Some portions of the
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* hardware support a block width of two gobs, but it is impractical
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* to use due to lack of support elsewhere, and has no known
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* benefits.
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*
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* 11:9 - Reserved (To support 2D-array textures with variable array stride
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* in blocks, specified via log2(tile width in blocks)). Must be
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* zero.
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*
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* 19:12 k Page Kind. This value directly maps to a field in the page
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* tables of all GPUs >= NV50. It affects the exact layout of bits
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* in memory and can be derived from the tuple
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*
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* (format, GPU model, compression type, samples per pixel)
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*
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* Where compression type is defined below. If GPU model were
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* implied by the format modifier, format, or memory buffer, page
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* kind would not need to be included in the modifier itself, but
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* since the modifier should define the layout of the associated
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* memory buffer independent from any device or other context, it
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* must be included here.
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*
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* 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
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* starting with Fermi GPUs. Additionally, the mapping between page
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* kind and bit layout has changed at various points.
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*
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* 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
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* 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
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* 2 = Gob Height 8, Turing+ Page Kind mapping
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* 3 = Reserved for future use.
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*
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* 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
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* bit remapping step that occurs at an even lower level than the
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* page kind and block linear swizzles. This causes the layout of
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* surfaces mapped in those SOC's GPUs to be incompatible with the
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* equivalent mapping on other GPUs in the same system.
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*
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* 0 = Tegra K1 - Tegra Parker/TX2 Layout.
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* 1 = Desktop GPU and Tegra Xavier+ Layout
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*
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* 25:23 c Lossless Framebuffer Compression type.
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*
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* 0 = none
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* 1 = ROP/3D, layout 1, exact compression format implied by Page
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* Kind field
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* 2 = ROP/3D, layout 2, exact compression format implied by Page
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* Kind field
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* 3 = CDE horizontal
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* 4 = CDE vertical
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* 5 = Reserved for future use
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* 6 = Reserved for future use
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* 7 = Reserved for future use
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*
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* 55:25 - Reserved for future use. Must be zero.
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*/
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#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
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fourcc_mod_code(NVIDIA, (0x10 | \
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((h) & 0xf) | \
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(((k) & 0xff) << 12) | \
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(((g) & 0x3) << 20) | \
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(((s) & 0x1) << 22) | \
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(((c) & 0x7) << 23)))
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/* To grandfather in prior block linear format modifiers to the above layout,
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* the page kind "0", which corresponds to "pitch/linear" and hence is unusable
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* with block-linear layouts, is remapped within drivers to the value 0xfe,
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* which corresponds to the "generic" kind used for simple single-sample
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* uncompressed color formats on Fermi - Volta GPUs.
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*/
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static __inline__ __u64
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drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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{
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if (!(modifier & 0x10) || (modifier & (0xff << 12)))
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return modifier;
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else
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return modifier | (0xfe << 12);
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}
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/*
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* 16Bx2 Block Linear layout, used by Tegra K1 and later
|
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*
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* Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
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* vertically by a power of 2 (1 to 32 GOBs) to form a block.
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|
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@ -518,20 +741,20 @@ extern "C" {
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* in full detail.
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*/
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
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fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
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DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
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#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
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fourcc_mod_code(NVIDIA, 0x10)
|
||||
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
|
||||
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
|
||||
fourcc_mod_code(NVIDIA, 0x11)
|
||||
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
|
||||
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
|
||||
fourcc_mod_code(NVIDIA, 0x12)
|
||||
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
|
||||
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
|
||||
fourcc_mod_code(NVIDIA, 0x13)
|
||||
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
|
||||
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
|
||||
fourcc_mod_code(NVIDIA, 0x14)
|
||||
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
|
||||
#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
|
||||
fourcc_mod_code(NVIDIA, 0x15)
|
||||
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
|
||||
|
||||
/*
|
||||
* Some Broadcom modifiers take parameters, for example the number of
|
||||
|
|
@ -648,7 +871,21 @@ extern "C" {
|
|||
* Further information on the use of AFBC modifiers can be found in
|
||||
* Documentation/gpu/afbc.rst
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
|
||||
|
||||
/*
|
||||
* The top 4 bits (out of the 56 bits alloted for specifying vendor specific
|
||||
* modifiers) denote the category for modifiers. Currently we have only two
|
||||
* categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
|
||||
* different categories.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
|
||||
fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
|
||||
|
||||
#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
|
||||
#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
|
||||
|
||||
#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
|
||||
DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
|
||||
|
||||
/*
|
||||
* AFBC superblock size
|
||||
|
|
@ -742,6 +979,28 @@ extern "C" {
|
|||
*/
|
||||
#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
|
||||
|
||||
/* AFBC uncompressed storage mode
|
||||
*
|
||||
* Indicates that the buffer is using AFBC uncompressed storage mode.
|
||||
* In this mode all superblock payloads in the buffer use the uncompressed
|
||||
* storage mode, which is usually only used for data which cannot be compressed.
|
||||
* The buffer layout is the same as for AFBC buffers without USM set, this only
|
||||
* affects the storage mode of the individual superblocks. Note that even a
|
||||
* buffer without USM set may use uncompressed storage mode for some or all
|
||||
* superblocks, USM just guarantees it for all.
|
||||
*/
|
||||
#define AFBC_FORMAT_MOD_USM (1ULL << 12)
|
||||
|
||||
/*
|
||||
* Arm 16x16 Block U-Interleaved modifier
|
||||
*
|
||||
* This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
|
||||
* into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
|
||||
* in the block are reordered.
|
||||
*/
|
||||
#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
|
||||
DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
|
||||
|
||||
/*
|
||||
* Allwinner tiled modifier
|
||||
*
|
||||
|
|
@ -756,6 +1015,220 @@ extern "C" {
|
|||
*/
|
||||
#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
|
||||
|
||||
/*
|
||||
* Amlogic Video Framebuffer Compression modifiers
|
||||
*
|
||||
* Amlogic uses a proprietary lossless image compression protocol and format
|
||||
* for their hardware video codec accelerators, either video decoders or
|
||||
* video input encoders.
|
||||
*
|
||||
* It considerably reduces memory bandwidth while writing and reading
|
||||
* frames in memory.
|
||||
*
|
||||
* The underlying storage is considered to be 3 components, 8bit or 10-bit
|
||||
* per component YCbCr 420, single plane :
|
||||
* - DRM_FORMAT_YUV420_8BIT
|
||||
* - DRM_FORMAT_YUV420_10BIT
|
||||
*
|
||||
* The first 8 bits of the mode defines the layout, then the following 8 bits
|
||||
* defines the options changing the layout.
|
||||
*
|
||||
* Not all combinations are valid, and different SoCs may support different
|
||||
* combinations of layout and options.
|
||||
*/
|
||||
#define __fourcc_mod_amlogic_layout_mask 0xf
|
||||
#define __fourcc_mod_amlogic_options_shift 8
|
||||
#define __fourcc_mod_amlogic_options_mask 0xf
|
||||
|
||||
#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
|
||||
fourcc_mod_code(AMLOGIC, \
|
||||
((__layout) & __fourcc_mod_amlogic_layout_mask) | \
|
||||
(((__options) & __fourcc_mod_amlogic_options_mask) \
|
||||
<< __fourcc_mod_amlogic_options_shift))
|
||||
|
||||
/* Amlogic FBC Layouts */
|
||||
|
||||
/*
|
||||
* Amlogic FBC Basic Layout
|
||||
*
|
||||
* The basic layout is composed of:
|
||||
* - a body content organized in 64x32 superblocks with 4096 bytes per
|
||||
* superblock in default mode.
|
||||
* - a 32 bytes per 128x64 header block
|
||||
*
|
||||
* This layout is transferrable between Amlogic SoCs supporting this modifier.
|
||||
*/
|
||||
#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
|
||||
|
||||
/*
|
||||
* Amlogic FBC Scatter Memory layout
|
||||
*
|
||||
* Indicates the header contains IOMMU references to the compressed
|
||||
* frames content to optimize memory access and layout.
|
||||
*
|
||||
* In this mode, only the header memory address is needed, thus the
|
||||
* content memory organization is tied to the current producer
|
||||
* execution and cannot be saved/dumped neither transferrable between
|
||||
* Amlogic SoCs supporting this modifier.
|
||||
*
|
||||
* Due to the nature of the layout, these buffers are not expected to
|
||||
* be accessible by the user-space clients, but only accessible by the
|
||||
* hardware producers and consumers.
|
||||
*
|
||||
* The user-space clients should expect a failure while trying to mmap
|
||||
* the DMA-BUF handle returned by the producer.
|
||||
*/
|
||||
#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
|
||||
|
||||
/* Amlogic FBC Layout Options Bit Mask */
|
||||
|
||||
/*
|
||||
* Amlogic FBC Memory Saving mode
|
||||
*
|
||||
* Indicates the storage is packed when pixel size is multiple of word
|
||||
* boudaries, i.e. 8bit should be stored in this mode to save allocation
|
||||
* memory.
|
||||
*
|
||||
* This mode reduces body layout to 3072 bytes per 64x32 superblock with
|
||||
* the basic layout and 3200 bytes per 64x32 superblock combined with
|
||||
* the scatter layout.
|
||||
*/
|
||||
#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
|
||||
|
||||
/*
|
||||
* AMD modifiers
|
||||
*
|
||||
* Memory layout:
|
||||
*
|
||||
* without DCC:
|
||||
* - main surface
|
||||
*
|
||||
* with DCC & without DCC_RETILE:
|
||||
* - main surface in plane 0
|
||||
* - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
|
||||
*
|
||||
* with DCC & DCC_RETILE:
|
||||
* - main surface in plane 0
|
||||
* - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
|
||||
* - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
|
||||
*
|
||||
* For multi-plane formats the above surfaces get merged into one plane for
|
||||
* each format plane, based on the required alignment only.
|
||||
*
|
||||
* Bits Parameter Notes
|
||||
* ----- ------------------------ ---------------------------------------------
|
||||
*
|
||||
* 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
|
||||
* 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
|
||||
* 13 DCC
|
||||
* 14 DCC_RETILE
|
||||
* 15 DCC_PIPE_ALIGN
|
||||
* 16 DCC_INDEPENDENT_64B
|
||||
* 17 DCC_INDEPENDENT_128B
|
||||
* 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
|
||||
* 20 DCC_CONSTANT_ENCODE
|
||||
* 23:21 PIPE_XOR_BITS Only for some chips
|
||||
* 26:24 BANK_XOR_BITS Only for some chips
|
||||
* 29:27 PACKERS Only for some chips
|
||||
* 32:30 RB Only for some chips
|
||||
* 35:33 PIPE Only for some chips
|
||||
* 55:36 - Reserved for future use, must be zero
|
||||
*/
|
||||
#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
|
||||
|
||||
#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
|
||||
|
||||
/* Reserve 0 for GFX8 and older */
|
||||
#define AMD_FMT_MOD_TILE_VER_GFX9 1
|
||||
#define AMD_FMT_MOD_TILE_VER_GFX10 2
|
||||
#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
|
||||
|
||||
/*
|
||||
* 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
|
||||
* version.
|
||||
*/
|
||||
#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
|
||||
|
||||
/*
|
||||
* 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
|
||||
* GFX9 as canonical version.
|
||||
*/
|
||||
#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
|
||||
#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
|
||||
#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
|
||||
#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
|
||||
|
||||
#define AMD_FMT_MOD_DCC_BLOCK_64B 0
|
||||
#define AMD_FMT_MOD_DCC_BLOCK_128B 1
|
||||
#define AMD_FMT_MOD_DCC_BLOCK_256B 2
|
||||
|
||||
#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
|
||||
#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
|
||||
#define AMD_FMT_MOD_TILE_SHIFT 8
|
||||
#define AMD_FMT_MOD_TILE_MASK 0x1F
|
||||
|
||||
/* Whether DCC compression is enabled. */
|
||||
#define AMD_FMT_MOD_DCC_SHIFT 13
|
||||
#define AMD_FMT_MOD_DCC_MASK 0x1
|
||||
|
||||
/*
|
||||
* Whether to include two DCC surfaces, one which is rb & pipe aligned, and
|
||||
* one which is not-aligned.
|
||||
*/
|
||||
#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
|
||||
#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
|
||||
|
||||
/* Only set if DCC_RETILE = false */
|
||||
#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
|
||||
#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
|
||||
|
||||
#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
|
||||
#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
|
||||
#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
|
||||
#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
|
||||
#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
|
||||
#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
|
||||
|
||||
/*
|
||||
* DCC supports embedding some clear colors directly in the DCC surface.
|
||||
* However, on older GPUs the rendering HW ignores the embedded clear color
|
||||
* and prefers the driver provided color. This necessitates doing a fastclear
|
||||
* eliminate operation before a process transfers control.
|
||||
*
|
||||
* If this bit is set that means the fastclear eliminate is not needed for these
|
||||
* embeddable colors.
|
||||
*/
|
||||
#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
|
||||
#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
|
||||
|
||||
/*
|
||||
* The below fields are for accounting for per GPU differences. These are only
|
||||
* relevant for GFX9 and later and if the tile field is *_X/_T.
|
||||
*
|
||||
* PIPE_XOR_BITS = always needed
|
||||
* BANK_XOR_BITS = only for TILE_VER_GFX9
|
||||
* PACKERS = only for TILE_VER_GFX10_RBPLUS
|
||||
* RB = only for TILE_VER_GFX9 & DCC
|
||||
* PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
|
||||
*/
|
||||
#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
|
||||
#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
|
||||
#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
|
||||
#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
|
||||
#define AMD_FMT_MOD_PACKERS_SHIFT 27
|
||||
#define AMD_FMT_MOD_PACKERS_MASK 0x7
|
||||
#define AMD_FMT_MOD_RB_SHIFT 30
|
||||
#define AMD_FMT_MOD_RB_MASK 0x7
|
||||
#define AMD_FMT_MOD_PIPE_SHIFT 33
|
||||
#define AMD_FMT_MOD_PIPE_MASK 0x7
|
||||
|
||||
#define AMD_FMT_MOD_SET(field, value) \
|
||||
((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
|
||||
#define AMD_FMT_MOD_GET(field, value) \
|
||||
(((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
|
||||
#define AMD_FMT_MOD_CLEAR(field) \
|
||||
(~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -33,6 +33,15 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* DOC: overview
|
||||
*
|
||||
* DRM exposes many UAPI and structure definition to have a consistent
|
||||
* and standardized interface with user.
|
||||
* Userspace can refer to these structure definitions and UAPI formats
|
||||
* to communicate to driver
|
||||
*/
|
||||
|
||||
#define DRM_CONNECTOR_NAME_LEN 32
|
||||
#define DRM_DISPLAY_MODE_LEN 32
|
||||
#define DRM_PROP_NAME_LEN 32
|
||||
|
|
@ -323,14 +332,19 @@ struct drm_mode_get_encoder {
|
|||
/* This is for connectors with multiple signal types. */
|
||||
/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
|
||||
enum drm_mode_subconnector {
|
||||
DRM_MODE_SUBCONNECTOR_Automatic = 0,
|
||||
DRM_MODE_SUBCONNECTOR_Unknown = 0,
|
||||
DRM_MODE_SUBCONNECTOR_DVID = 3,
|
||||
DRM_MODE_SUBCONNECTOR_DVIA = 4,
|
||||
DRM_MODE_SUBCONNECTOR_Composite = 5,
|
||||
DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
|
||||
DRM_MODE_SUBCONNECTOR_Component = 8,
|
||||
DRM_MODE_SUBCONNECTOR_SCART = 9,
|
||||
DRM_MODE_SUBCONNECTOR_Automatic = 0, /* DVI-I, TV */
|
||||
DRM_MODE_SUBCONNECTOR_Unknown = 0, /* DVI-I, TV, DP */
|
||||
DRM_MODE_SUBCONNECTOR_VGA = 1, /* DP */
|
||||
DRM_MODE_SUBCONNECTOR_DVID = 3, /* DVI-I DP */
|
||||
DRM_MODE_SUBCONNECTOR_DVIA = 4, /* DVI-I */
|
||||
DRM_MODE_SUBCONNECTOR_Composite = 5, /* TV */
|
||||
DRM_MODE_SUBCONNECTOR_SVIDEO = 6, /* TV */
|
||||
DRM_MODE_SUBCONNECTOR_Component = 8, /* TV */
|
||||
DRM_MODE_SUBCONNECTOR_SCART = 9, /* TV */
|
||||
DRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */
|
||||
DRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */
|
||||
DRM_MODE_SUBCONNECTOR_Native = 15, /* DP */
|
||||
DRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */
|
||||
};
|
||||
|
||||
#define DRM_MODE_CONNECTOR_Unknown 0
|
||||
|
|
@ -352,6 +366,7 @@ enum drm_mode_subconnector {
|
|||
#define DRM_MODE_CONNECTOR_DSI 16
|
||||
#define DRM_MODE_CONNECTOR_DPI 17
|
||||
#define DRM_MODE_CONNECTOR_WRITEBACK 18
|
||||
#define DRM_MODE_CONNECTOR_SPI 19
|
||||
|
||||
struct drm_mode_get_connector {
|
||||
|
||||
|
|
@ -487,7 +502,7 @@ struct drm_mode_fb_cmd2 {
|
|||
* In case of planar formats, this ioctl allows up to 4
|
||||
* buffer objects with offsets and pitches per plane.
|
||||
* The pitch and offset order is dictated by the fourcc,
|
||||
* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
|
||||
* e.g. NV12 (https://fourcc.org/yuv.php#NV12) is described as:
|
||||
*
|
||||
* YUV 4:2:0 image with a plane of 8 bit Y samples
|
||||
* followed by an interleaved U/V plane containing
|
||||
|
|
@ -630,6 +645,92 @@ struct drm_color_lut {
|
|||
__u16 reserved;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hdr_metadata_infoframe - HDR Metadata Infoframe Data.
|
||||
*
|
||||
* HDR Metadata Infoframe as per CTA 861.G spec. This is expected
|
||||
* to match exactly with the spec.
|
||||
*
|
||||
* Userspace is expected to pass the metadata information as per
|
||||
* the format described in this structure.
|
||||
*/
|
||||
struct hdr_metadata_infoframe {
|
||||
/**
|
||||
* @eotf: Electro-Optical Transfer Function (EOTF)
|
||||
* used in the stream.
|
||||
*/
|
||||
__u8 eotf;
|
||||
/**
|
||||
* @metadata_type: Static_Metadata_Descriptor_ID.
|
||||
*/
|
||||
__u8 metadata_type;
|
||||
/**
|
||||
* @display_primaries: Color Primaries of the Data.
|
||||
* These are coded as unsigned 16-bit values in units of
|
||||
* 0.00002, where 0x0000 represents zero and 0xC350
|
||||
* represents 1.0000.
|
||||
* @display_primaries.x: X cordinate of color primary.
|
||||
* @display_primaries.y: Y cordinate of color primary.
|
||||
*/
|
||||
struct {
|
||||
__u16 x, y;
|
||||
} display_primaries[3];
|
||||
/**
|
||||
* @white_point: White Point of Colorspace Data.
|
||||
* These are coded as unsigned 16-bit values in units of
|
||||
* 0.00002, where 0x0000 represents zero and 0xC350
|
||||
* represents 1.0000.
|
||||
* @white_point.x: X cordinate of whitepoint of color primary.
|
||||
* @white_point.y: Y cordinate of whitepoint of color primary.
|
||||
*/
|
||||
struct {
|
||||
__u16 x, y;
|
||||
} white_point;
|
||||
/**
|
||||
* @max_display_mastering_luminance: Max Mastering Display Luminance.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
__u16 max_display_mastering_luminance;
|
||||
/**
|
||||
* @min_display_mastering_luminance: Min Mastering Display Luminance.
|
||||
* This value is coded as an unsigned 16-bit value in units of
|
||||
* 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF
|
||||
* represents 6.5535 cd/m2.
|
||||
*/
|
||||
__u16 min_display_mastering_luminance;
|
||||
/**
|
||||
* @max_cll: Max Content Light Level.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
__u16 max_cll;
|
||||
/**
|
||||
* @max_fall: Max Frame Average Light Level.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
__u16 max_fall;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct hdr_output_metadata - HDR output metadata
|
||||
*
|
||||
* Metadata Information to be passed from userspace
|
||||
*/
|
||||
struct hdr_output_metadata {
|
||||
/**
|
||||
* @metadata_type: Static_Metadata_Descriptor_ID.
|
||||
*/
|
||||
__u32 metadata_type;
|
||||
/**
|
||||
* @hdmi_metadata_type1: HDR Metadata Infoframe.
|
||||
*/
|
||||
union {
|
||||
struct hdr_metadata_infoframe hdmi_metadata_type1;
|
||||
};
|
||||
};
|
||||
|
||||
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
|
||||
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
|
||||
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
|
||||
|
|
@ -803,6 +904,10 @@ struct drm_format_modifier {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_create_blob - Create New block property
|
||||
* @data: Pointer to data to copy.
|
||||
* @length: Length of data to copy.
|
||||
* @blob_id: new property ID.
|
||||
* Create a new 'blob' data property, copying length bytes from data pointer,
|
||||
* and returning new blob ID.
|
||||
*/
|
||||
|
|
@ -816,13 +921,27 @@ struct drm_mode_create_blob {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_destroy_blob - Destroy user blob
|
||||
* @blob_id: blob_id to destroy
|
||||
* Destroy a user-created blob property.
|
||||
*
|
||||
* User-space can release blobs as soon as they do not need to refer to them by
|
||||
* their blob object ID. For instance, if you are using a MODE_ID blob in an
|
||||
* atomic commit and you will not make another commit re-using the same ID, you
|
||||
* can destroy the blob as soon as the commit has been issued, without waiting
|
||||
* for it to complete.
|
||||
*/
|
||||
struct drm_mode_destroy_blob {
|
||||
__u32 blob_id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_create_lease - Create lease
|
||||
* @object_ids: Pointer to array of object ids.
|
||||
* @object_count: Number of object ids.
|
||||
* @flags: flags for new FD.
|
||||
* @lessee_id: unique identifier for lessee.
|
||||
* @fd: file descriptor to new drm_master file.
|
||||
* Lease mode resources, creating another drm_master.
|
||||
*/
|
||||
struct drm_mode_create_lease {
|
||||
|
|
@ -840,6 +959,10 @@ struct drm_mode_create_lease {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_list_lessees - List lessees
|
||||
* @count_lessees: Number of lessees.
|
||||
* @pad: pad.
|
||||
* @lessees_ptr: Pointer to lessess.
|
||||
* List lesses from a drm_master
|
||||
*/
|
||||
struct drm_mode_list_lessees {
|
||||
|
|
@ -860,6 +983,10 @@ struct drm_mode_list_lessees {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_get_lease - Get Lease
|
||||
* @count_objects: Number of leased objects.
|
||||
* @pad: pad.
|
||||
* @objects_ptr: Pointer to objects.
|
||||
* Get leased objects
|
||||
*/
|
||||
struct drm_mode_get_lease {
|
||||
|
|
@ -880,6 +1007,8 @@ struct drm_mode_get_lease {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_revoke_lease - Revoke lease
|
||||
* @lessee_id: Unique ID of lessee.
|
||||
* Revoke lease
|
||||
*/
|
||||
struct drm_mode_revoke_lease {
|
||||
|
|
|
|||
Loading…
Reference in New Issue