amdgpu: add ce_ram_size for interface query
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>main
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@ -520,6 +520,8 @@ struct amdgpu_gpu_info {
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uint32_t vram_type;
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uint32_t vram_type;
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/* video memory bit width*/
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/* video memory bit width*/
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uint32_t vram_bit_width;
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uint32_t vram_bit_width;
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/** constant engine ram size*/
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uint32_t ce_ram_size;
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};
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};
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@ -160,6 +160,7 @@ int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
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dev->dev_info.num_shader_arrays_per_engine;
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dev->dev_info.num_shader_arrays_per_engine;
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dev->info.vram_type = dev->dev_info.vram_type;
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dev->info.vram_type = dev->dev_info.vram_type;
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dev->info.vram_bit_width = dev->dev_info.vram_bit_width;
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dev->info.vram_bit_width = dev->dev_info.vram_bit_width;
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dev->info.ce_ram_size = dev->dev_info.ce_ram_size;
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for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
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for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
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unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
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unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
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@ -586,6 +586,8 @@ struct drm_amdgpu_info_device {
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uint32_t vram_type;
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uint32_t vram_type;
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/** video memory bit width*/
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/** video memory bit width*/
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uint32_t vram_bit_width;
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uint32_t vram_bit_width;
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/** constant engine ram size*/
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uint32_t ce_ram_size;
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};
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};
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struct drm_amdgpu_info_hw_ip {
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struct drm_amdgpu_info_hw_ip {
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