radeon: fix mipmap level 0 and 1 alignment for SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>main
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0c3fd8708f
commit
ce8af45425
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@ -1541,6 +1541,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
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uint64_t offset, unsigned start_level)
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uint64_t offset, unsigned start_level)
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{
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{
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uint32_t xalign, yalign, zalign, slice_align;
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uint32_t xalign, yalign, zalign, slice_align;
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unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
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unsigned i;
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unsigned i;
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/* compute alignment */
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/* compute alignment */
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@ -1552,11 +1553,11 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
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xalign = MAX2((bpe == 1) ? 64 : 32, xalign);
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xalign = MAX2((bpe == 1) ? 64 : 32, xalign);
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}
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}
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if (!start_level) {
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if (start_level <= 1) {
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surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
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surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
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if (offset) {
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if (offset) {
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offset = ALIGN(offset, surf->bo_alignment);
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offset = ALIGN(offset, alignment);
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}
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}
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}
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}
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@ -1567,7 +1568,7 @@ static int si_surface_init_1d(struct radeon_surface_manager *surf_man,
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/* level0 and first mipmap need to have alignment */
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/* level0 and first mipmap need to have alignment */
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offset = surf->bo_size;
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offset = surf->bo_size;
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if ((i == 0)) {
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if ((i == 0)) {
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offset = ALIGN(offset, surf->bo_alignment);
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offset = ALIGN(offset, alignment);
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}
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}
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if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
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if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
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if (surf->level == level) {
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if (surf->level == level) {
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@ -1609,6 +1610,7 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
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uint64_t offset,
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uint64_t offset,
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unsigned start_level)
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unsigned start_level)
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{
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{
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uint64_t aligned_offset = offset;
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unsigned tilew, tileh, tileb;
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unsigned tilew, tileh, tileb;
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unsigned mtilew, mtileh, mtileb;
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unsigned mtilew, mtileh, mtileb;
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unsigned slice_pt;
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unsigned slice_pt;
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@ -1632,19 +1634,19 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
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/* macro tile bytes */
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/* macro tile bytes */
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mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
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mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
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if (!start_level) {
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if (start_level <= 1) {
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unsigned alignment = MAX2(256, mtileb);
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unsigned alignment = MAX2(256, mtileb);
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surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
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surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
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if (offset) {
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if (aligned_offset) {
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offset = ALIGN(offset, alignment);
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aligned_offset = ALIGN(aligned_offset, alignment);
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}
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}
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}
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}
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/* build mipmap tree */
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/* build mipmap tree */
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for (i = start_level; i <= surf->last_level; i++) {
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for (i = start_level; i <= surf->last_level; i++) {
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level[i].mode = RADEON_SURF_MODE_2D;
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level[i].mode = RADEON_SURF_MODE_2D;
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si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, offset);
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si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
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if (level[i].mode == RADEON_SURF_MODE_1D) {
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if (level[i].mode == RADEON_SURF_MODE_1D) {
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switch (tile_mode) {
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switch (tile_mode) {
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case SI_TILE_MODE_COLOR_2D_8BPP:
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case SI_TILE_MODE_COLOR_2D_8BPP:
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@ -1669,9 +1671,9 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
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return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
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return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
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}
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}
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/* level0 and first mipmap need to have alignment */
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/* level0 and first mipmap need to have alignment */
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offset = surf->bo_size;
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aligned_offset = surf->bo_size;
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if ((i == 0)) {
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if ((i == 0)) {
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offset = ALIGN(offset, surf->bo_alignment);
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aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
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}
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}
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if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
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if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
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if (surf->level == level) {
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if (surf->level == level) {
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