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tests/amdgpu: enable vcn test based on ip query 

family_id checks can be removed and instead use ip major/minor version

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
main
Sathishkumar S 2022-02-10 19:19:50 +05:30 committed by Leo Liu
parent 1d92f32741
commit d13ab997f5
1 changed files with 28 additions and 53 deletions
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81
tests/amdgpu/vcn_tests.c
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@ -70,7 +70,13 @@ static uint32_t *ib_cpu;
static amdgpu_bo_handle resources[MAX_RESOURCES];
static unsigned num_resources;
static struct amdgpu_vcn_reg reg;
static uint8_t vcn_reg_index;
static struct amdgpu_vcn_reg reg[] = {
{0x81c4, 0x81c5, 0x81c3, 0x81ff, 0x81c6},
{0x504, 0x505, 0x503, 0x53f, 0x506},
{0x10, 0x11, 0xf, 0x29, 0x26d},
};
static void amdgpu_cs_vcn_dec_create(void);
static void amdgpu_cs_vcn_dec_decode(void);
@ -125,45 +131,14 @@ CU_BOOL suite_vcn_tests_enable(void)
amdgpu_set_test_active("VCN Tests", "VCN ENC destroy", CU_FALSE);
}
if (family_id == AMDGPU_FAMILY_RV) {
if (chip_id >= (chip_rev + 0x91)) {
reg.data0 = 0x504;
reg.data1 = 0x505;
reg.cmd = 0x503;
reg.nop = 0x53f;
reg.cntl = 0x506;
} else {
reg.data0 = 0x81c4;
reg.data1 = 0x81c5;
reg.cmd = 0x81c3;
reg.nop = 0x81ff;
reg.cntl = 0x81c6;
}
} else if (family_id == AMDGPU_FAMILY_NV) {
if (chip_id == (chip_rev + 0x28) ||
chip_id == (chip_rev + 0x32) ||
chip_id == (chip_rev + 0x3c) ||
chip_id == (chip_rev + 0x46)) {
reg.data0 = 0x10;
reg.data1 = 0x11;
reg.cmd = 0xf;
reg.nop = 0x29;
reg.cntl = 0x26d;
}
else {
reg.data0 = 0x504;
reg.data1 = 0x505;
reg.cmd = 0x503;
reg.nop = 0x53f;
reg.cntl = 0x506;
}
} else if (family_id == AMDGPU_FAMILY_AI) {
reg.data0 = 0x10;
reg.data1 = 0x11;
reg.cmd = 0xf;
reg.nop = 0x29;
reg.cntl = 0x26d;
} else
if (info.hw_ip_version_major == 1)
vcn_reg_index = 0;
else if (info.hw_ip_version_major == 2)
vcn_reg_index = 1;
else if ((info.hw_ip_version_major == 2 && info.hw_ip_version_minor >= 5) ||
info.hw_ip_version_major == 3)
vcn_reg_index = 2;
else
return CU_FALSE;
return CU_TRUE;
@ -307,11 +282,11 @@ static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
{
ib_cpu[(*idx)++] = reg.data0;
ib_cpu[(*idx)++] = reg[vcn_reg_index].data0;
ib_cpu[(*idx)++] = addr;
ib_cpu[(*idx)++] = reg.data1;
ib_cpu[(*idx)++] = reg[vcn_reg_index].data1;
ib_cpu[(*idx)++] = addr >> 32;
ib_cpu[(*idx)++] = reg.cmd;
ib_cpu[(*idx)++] = reg[vcn_reg_index].cmd;
ib_cpu[(*idx)++] = cmd << 1;
}
@ -332,14 +307,14 @@ static void amdgpu_cs_vcn_dec_create(void)
memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
len = 0;
ib_cpu[len++] = reg.data0;
ib_cpu[len++] = reg[vcn_reg_index].data0;
ib_cpu[len++] = msg_buf.addr;
ib_cpu[len++] = reg.data1;
ib_cpu[len++] = reg[vcn_reg_index].data1;
ib_cpu[len++] = msg_buf.addr >> 32;
ib_cpu[len++] = reg.cmd;
ib_cpu[len++] = reg[vcn_reg_index].cmd;
ib_cpu[len++] = 0;
for (; len % 16; ) {
ib_cpu[len++] = reg.nop;
ib_cpu[len++] = reg[vcn_reg_index].nop;
ib_cpu[len++] = 0;
}
@ -407,10 +382,10 @@ static void amdgpu_cs_vcn_dec_decode(void)
vcn_dec_cmd(it_addr, 0x204, &len);
vcn_dec_cmd(ctx_addr, 0x206, &len);
ib_cpu[len++] = reg.cntl;
ib_cpu[len++] = reg[vcn_reg_index].cntl;
ib_cpu[len++] = 0x1;
for (; len % 16; ) {
ib_cpu[len++] = reg.nop;
ib_cpu[len++] = reg[vcn_reg_index].nop;
ib_cpu[len++] = 0;
}
@ -442,14 +417,14 @@ static void amdgpu_cs_vcn_dec_destroy(void)
memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
len = 0;
ib_cpu[len++] = reg.data0;
ib_cpu[len++] = reg[vcn_reg_index].data0;
ib_cpu[len++] = msg_buf.addr;
ib_cpu[len++] = reg.data1;
ib_cpu[len++] = reg[vcn_reg_index].data1;
ib_cpu[len++] = msg_buf.addr >> 32;
ib_cpu[len++] = reg.cmd;
ib_cpu[len++] = reg[vcn_reg_index].cmd;
ib_cpu[len++] = 0;
for (; len % 16; ) {
ib_cpu[len++] = reg.nop;
ib_cpu[len++] = reg[vcn_reg_index].nop;
ib_cpu[len++] = 0;
}