Some code commenting concerning the FIFO & DMA engine.
Jose Fonseca
parent
7d0cb01cbf
commit
d29e2369be
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@ -1,6 +1,15 @@
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/* mach64_dma.c -- DMA support for mach64 (Rage Pro) driver -*- linux-c -*-
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* Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com
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/* mach64_dma.c -- DMA support for mach64 (Rage Pro) driver -*- linux-c -*- */
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/**
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* \file mach64_dma.c
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* DMA support for mach64 (Rage Pro) driver
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*
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* \author Gareth Hughes <gareth@valinux.com>
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* \author Frank C. Earl <fearl@airmail.net>
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* \author Leif Delgass <ldelgass@retinalburn.net>
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* \author Jose Fonseca <j_r_fonseca@yahoo.co.uk>
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*/
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/*
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* Copyright 2000 Gareth Hughes
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* Copyright 2002 Frank C. Earl
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* Copyright 2002-2003 Leif Delgass
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@ -23,12 +32,6 @@
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* THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Gareth Hughes <gareth@valinux.com>
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* Frank C. Earl <fearl@airmail.net>
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* Leif Delgass <ldelgass@retinalburn.net>
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* Jos<EFBFBD>Fonseca <j_r_fonseca@yahoo.co.uk>
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*/
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#include "drmP.h"
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@ -36,10 +39,24 @@
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#include "mach64_drm.h"
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#include "mach64_drv.h"
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/* ================================================================
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* Engine, FIFO control
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*/
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/*******************************************************************/
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/** \name Engine, FIFO control */
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/*@{*/
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/**
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* Waits for free entries in the FIFO.
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*
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* \note Most writes to Mach64 registers are automatically routed through
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* command FIFO which is 16 entry deep. Prior to writing to any draw engine
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* register one has to ensure that enough FIFO entries are available by calling
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* this function. Failure to do so may cause the engine to lock.
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*
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* \param dev_priv pointer to device private data structure.
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* \param entries number of free entries in the FIFO to wait for.
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*
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* \returns zero on success, or -EBUSY if the timeout (specificed by
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* drm_mach64_private::usec_timeout) occurs.
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*/
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int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, int entries)
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{
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int slots = 0, i;
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@ -56,6 +73,9 @@ int mach64_do_wait_for_fifo(drm_mach64_private_t * dev_priv, int entries)
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return DRM_ERR(EBUSY);
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}
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/**
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* Wait for the draw engine to be idle.
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*/
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int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv)
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{
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int i, ret;
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@ -77,6 +97,25 @@ int mach64_do_wait_for_idle(drm_mach64_private_t * dev_priv)
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return DRM_ERR(EBUSY);
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}
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/**
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* Wait for free entries in the ring buffer.
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*
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* The Mach64 bus master can be configured to act as a virtual FIFO, using a
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* circular buffer (commonly referred as "ring buffer" in other drivers) with
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* pointers to engine commands. This allows the CPU to do other things while
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* the graphics engine is busy, i.e., DMA mode.
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*
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* This function should be called before writing new entries to the ring
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* buffer.
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*
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* \param dev_priv pointer to device private data structure.
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* \param n number of free entries in the ring buffer to wait for.
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*
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* \returns zero on success, or -EBUSY if the timeout (specificed by
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* drm_mach64_private_t::usec_timeout) occurs.
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*
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* \sa mach64_dump_ring_info()
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*/
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int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n)
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{
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drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
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@ -99,7 +138,11 @@ int mach64_wait_ring(drm_mach64_private_t * dev_priv, int n)
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return DRM_ERR(EBUSY);
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}
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/* Wait until all DMA requests have been processed... */
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/**
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* Wait until all DMA requests have been processed...
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*
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* \sa mach64_wait_ring()
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*/
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static int mach64_ring_idle(drm_mach64_private_t * dev_priv)
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{
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drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
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@ -132,6 +175,11 @@ static int mach64_ring_idle(drm_mach64_private_t * dev_priv)
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return DRM_ERR(EBUSY);
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}
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/**
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* Reset the the ring buffer descriptors.
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*
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* \sa mach64_do_engine_reset()
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*/
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static void mach64_ring_reset(drm_mach64_private_t * dev_priv)
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{
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drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
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@ -147,6 +195,9 @@ static void mach64_ring_reset(drm_mach64_private_t * dev_priv)
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dev_priv->ring_running = 0;
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}
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/**
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* Ensure the all the queued commands will be processed.
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*/
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int mach64_do_dma_flush(drm_mach64_private_t * dev_priv)
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{
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/* FIXME: It's not necessary to wait for idle when flushing
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@ -156,6 +207,9 @@ int mach64_do_dma_flush(drm_mach64_private_t * dev_priv)
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return mach64_ring_idle(dev_priv);
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}
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/**
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* Stop all DMA activity.
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*/
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int mach64_do_dma_idle(drm_mach64_private_t * dev_priv)
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{
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int ret;
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@ -175,7 +229,8 @@ int mach64_do_dma_idle(drm_mach64_private_t * dev_priv)
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return 0;
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}
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/* Reset the engine. This will stop the DMA if it is running.
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/**
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* Reset the engine. This will stop the DMA if it is running.
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*/
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int mach64_do_engine_reset(drm_mach64_private_t * dev_priv)
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{
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@ -211,10 +266,16 @@ int mach64_do_engine_reset(drm_mach64_private_t * dev_priv)
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return 0;
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}
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/* ================================================================
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* Debugging output
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*/
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/*@}*/
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/*******************************************************************/
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/** \name Debugging output */
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/*@{*/
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/**
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* Dump engine registers values.
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*/
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void mach64_dump_engine_info(drm_mach64_private_t * dev_priv)
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{
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DRM_INFO("\n");
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@ -352,6 +413,10 @@ void mach64_dump_engine_info(drm_mach64_private_t * dev_priv)
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#define MACH64_DUMP_CONTEXT 3
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/**
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* Used by mach64_dump_ring_info() to dump the contents of the current buffer
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* pointed by the ring head.
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*/
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static void mach64_dump_buf_info(drm_mach64_private_t * dev_priv,
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drm_buf_t * buf)
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{
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@ -408,6 +473,10 @@ static void mach64_dump_buf_info(drm_mach64_private_t * dev_priv,
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DRM_INFO("\n");
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}
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/**
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* Dump the ring state and contents, including the contents of the buffer being
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* processed by the graphics engine.
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*/
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void mach64_dump_ring_info(drm_mach64_private_t * dev_priv)
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{
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drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
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@ -486,10 +555,23 @@ void mach64_dump_ring_info(drm_mach64_private_t * dev_priv)
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MACH64_READ(MACH64_SRC_CNTL));
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}
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/* ================================================================
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* DMA test and initialization
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*/
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/*@}*/
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/*******************************************************************/
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/** \name DMA test and initialization */
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/*@{*/
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/**
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* Perform a simple DMA operation using the pattern registers to test whether
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* DMA works.
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*
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* \return zero if successful.
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*
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* \note This function was the testbed for many experiences regarding Mach64
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* DMA operation. It is left here since it so tricky to get DMA operating
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* properly in some architectures and hardware.
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*/
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static int mach64_bm_dma_test(drm_device_t * dev)
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{
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drm_mach64_private_t *dev_priv = dev->dev_private;
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@ -667,6 +749,10 @@ static int mach64_bm_dma_test(drm_device_t * dev)
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return failed;
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}
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/**
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* Called during the DMA initialization ioctl to initialize all the necessary
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* software and hardware state for DMA operation.
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*/
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static int mach64_do_dma_init(drm_device_t * dev, drm_mach64_init_t * init)
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{
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drm_mach64_private_t *dev_priv;
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@ -895,8 +981,8 @@ static int mach64_do_dma_init(drm_device_t * dev, drm_mach64_init_t * init)
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return 0;
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}
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/* ===================================================================
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* MMIO Pseudo-DMA (intended primarily for debugging, not performance)
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/*******************************************************************/
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/** MMIO Pseudo-DMA (intended primarily for debugging, not performance)
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*/
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int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv)
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@ -1041,9 +1127,12 @@ int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t * dev_priv)
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return 0;
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}
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/* ================================================================
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* DMA cleanup
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*/
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/*@}*/
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/*******************************************************************/
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/** \name DMA cleanup */
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/*@{*/
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int mach64_do_cleanup_dma(drm_device_t * dev)
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{
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@ -1086,9 +1175,12 @@ int mach64_do_cleanup_dma(drm_device_t * dev)
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return 0;
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}
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/* ================================================================
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* IOCTL handlers
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*/
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/*@}*/
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/*******************************************************************/
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/** \name IOCTL handlers */
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/*@{*/
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int mach64_dma_init(DRM_IOCTL_ARGS)
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{
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@ -1148,9 +1240,12 @@ int mach64_engine_reset(DRM_IOCTL_ARGS)
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return mach64_do_engine_reset(dev_priv);
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}
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/* ================================================================
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* Freelist management
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*/
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/*@}*/
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/*******************************************************************/
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/** \name Freelist management */
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/*@{*/
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int mach64_init_freelist(drm_device_t * dev)
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{
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@ -1351,9 +1446,12 @@ drm_buf_t *mach64_freelist_get(drm_mach64_private_t * dev_priv)
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return entry->buf;
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}
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/* ================================================================
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* DMA buffer request and submission IOCTL handler
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*/
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/*@}*/
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/*******************************************************************/
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/** \name DMA buffer request and submission IOCTL handler */
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/*@{*/
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static int mach64_dma_get_buffers(DRMFILE filp, drm_device_t * dev,
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drm_dma_t * d)
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@ -1428,3 +1526,5 @@ void mach64_driver_pretakedown(drm_device_t * dev)
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{
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mach64_do_cleanup_dma(dev);
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}
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/*@}*/
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