get rid of superfluous fields in struct drm_radeon_ring_buffer
use correct address for ring read pointer writeback (yes, we seem to have
been running with bogus values for the ring read pointer, which
'worked' because the return value of radeon_wait_ring() is never
checked and the ring usually never fills up)
main
Michel Daenzer
parent
5ee61c18f4
commit
d5db1144dd
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@ -771,7 +771,7 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
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cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
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RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
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*dev_priv->ring.head = cur_read_ptr;
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SET_RING_HEAD( dev_priv, cur_read_ptr );
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dev_priv->ring.tail = cur_read_ptr;
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}
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@ -883,13 +883,18 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
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/* Initialize the ring buffer's read and write pointers */
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cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
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RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
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*dev_priv->ring.head = cur_read_ptr;
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SET_RING_HEAD( dev_priv, cur_read_ptr );
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dev_priv->ring.tail = cur_read_ptr;
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#if __REALLY_HAVE_AGP
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if ( !dev_priv->is_pci ) {
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RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
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dev_priv->ring_rptr->offset );
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} else {
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dev_priv->ring_rptr->offset
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- dev->agp->base
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+ dev_priv->agp_vm_start);
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} else
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#endif
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{
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drm_sg_mem_t *entry = dev->sg;
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unsigned long tmp_ofs, page_ofs;
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@ -914,7 +919,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
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+ RADEON_SCRATCH_REG_OFFSET );
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dev_priv->scratch = ((__volatile__ u32 *)
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dev_priv->ring.head +
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dev_priv->ring_rptr->handle +
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(RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
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RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
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@ -1194,9 +1199,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
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dev_priv->agp_buffers_offset );
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dev_priv->ring.head = ((__volatile__ u32 *)
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dev_priv->ring_rptr->handle);
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dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
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dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
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+ init->ring_size / sizeof(u32));
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@ -1207,7 +1209,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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(dev_priv->ring.size / sizeof(u32)) - 1;
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dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
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dev_priv->ring.ring_rptr = dev_priv->ring_rptr;
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#if __REALLY_HAVE_SG
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if ( dev_priv->is_pci ) {
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@ -1585,10 +1586,10 @@ int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
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{
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drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
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int i;
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u32 last_head = GET_RING_HEAD(ring);
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u32 last_head = GET_RING_HEAD( dev_priv );
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for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
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u32 head = GET_RING_HEAD(ring);
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u32 head = GET_RING_HEAD( dev_priv );
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ring->space = (head - ring->tail) * sizeof(u32);
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if ( ring->space <= 0 )
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@ -31,8 +31,8 @@
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#ifndef __RADEON_DRV_H__
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#define __RADEON_DRV_H__
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#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */
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#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */
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#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
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#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
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typedef struct drm_radeon_freelist {
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unsigned int age;
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@ -47,13 +47,11 @@ typedef struct drm_radeon_ring_buffer {
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int size;
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int size_l2qw;
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volatile u32 *head;
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u32 tail;
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u32 tail_mask;
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int space;
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int high_mark;
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drm_local_map_t *ring_rptr;
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} drm_radeon_ring_buffer_t;
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typedef struct drm_radeon_depth_clear_t {
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@ -782,7 +780,7 @@ extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
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#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
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do { \
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if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
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u32 head = GET_RING_HEAD(&dev_priv->ring); \
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u32 head = GET_RING_HEAD( dev_priv ); \
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if (head == dev_priv->ring.tail) \
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dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
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} \
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@ -854,8 +852,8 @@ do { \
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#define COMMIT_RING() do { \
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/* Flush writes to ring */ \
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DRM_READMEMORYBARRIER(dev_priv->mmio); \
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GET_RING_HEAD( &dev_priv->ring ); \
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DRM_READMEMORYBARRIER( dev_priv->mmio ); \
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GET_RING_HEAD( dev_priv ); \
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RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
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/* read from PCI bus to ensure correct posting */ \
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RADEON_READ( RADEON_CP_RB_RPTR ); \
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@ -771,7 +771,7 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
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cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
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RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
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*dev_priv->ring.head = cur_read_ptr;
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SET_RING_HEAD( dev_priv, cur_read_ptr );
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dev_priv->ring.tail = cur_read_ptr;
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}
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@ -883,13 +883,18 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
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/* Initialize the ring buffer's read and write pointers */
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cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
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RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
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*dev_priv->ring.head = cur_read_ptr;
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SET_RING_HEAD( dev_priv, cur_read_ptr );
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dev_priv->ring.tail = cur_read_ptr;
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#if __REALLY_HAVE_AGP
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if ( !dev_priv->is_pci ) {
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RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
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dev_priv->ring_rptr->offset );
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} else {
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dev_priv->ring_rptr->offset
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- dev->agp->base
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+ dev_priv->agp_vm_start);
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} else
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#endif
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{
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drm_sg_mem_t *entry = dev->sg;
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unsigned long tmp_ofs, page_ofs;
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@ -914,7 +919,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
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+ RADEON_SCRATCH_REG_OFFSET );
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dev_priv->scratch = ((__volatile__ u32 *)
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dev_priv->ring.head +
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dev_priv->ring_rptr->handle +
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(RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
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RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
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@ -1194,9 +1199,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
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dev_priv->agp_buffers_offset );
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dev_priv->ring.head = ((__volatile__ u32 *)
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dev_priv->ring_rptr->handle);
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dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
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dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
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+ init->ring_size / sizeof(u32));
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@ -1207,7 +1209,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
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(dev_priv->ring.size / sizeof(u32)) - 1;
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dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
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dev_priv->ring.ring_rptr = dev_priv->ring_rptr;
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#if __REALLY_HAVE_SG
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if ( dev_priv->is_pci ) {
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@ -1585,10 +1586,10 @@ int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
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{
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drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
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int i;
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u32 last_head = GET_RING_HEAD(ring);
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u32 last_head = GET_RING_HEAD( dev_priv );
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for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
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u32 head = GET_RING_HEAD(ring);
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u32 head = GET_RING_HEAD( dev_priv );
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ring->space = (head - ring->tail) * sizeof(u32);
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if ( ring->space <= 0 )
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@ -31,8 +31,8 @@
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#ifndef __RADEON_DRV_H__
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#define __RADEON_DRV_H__
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#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */
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#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */
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#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
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#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
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typedef struct drm_radeon_freelist {
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unsigned int age;
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@ -47,13 +47,11 @@ typedef struct drm_radeon_ring_buffer {
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int size;
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int size_l2qw;
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volatile u32 *head;
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u32 tail;
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u32 tail_mask;
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int space;
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int high_mark;
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drm_local_map_t *ring_rptr;
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} drm_radeon_ring_buffer_t;
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typedef struct drm_radeon_depth_clear_t {
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@ -782,7 +780,7 @@ extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
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#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
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do { \
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if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
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u32 head = GET_RING_HEAD(&dev_priv->ring); \
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u32 head = GET_RING_HEAD( dev_priv ); \
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if (head == dev_priv->ring.tail) \
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dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
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} \
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@ -854,8 +852,8 @@ do { \
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#define COMMIT_RING() do { \
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/* Flush writes to ring */ \
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DRM_READMEMORYBARRIER(dev_priv->mmio); \
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GET_RING_HEAD( &dev_priv->ring ); \
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DRM_READMEMORYBARRIER( dev_priv->mmio ); \
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GET_RING_HEAD( dev_priv ); \
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RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
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/* read from PCI bus to ensure correct posting */ \
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RADEON_READ( RADEON_CP_RB_RPTR ); \
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