First pass of 4.1.0 merge.
David Dawes
parent
334e134918
commit
d87c873df0
|
|
@ -27,7 +27,7 @@
|
|||
* Authors: Rickard E. (Rik) Faith <faith@valinux.com>
|
||||
* Kevin E. Martin <martin@valinux.com>
|
||||
*
|
||||
* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drm.c,v 1.20 2001/04/18 18:44:39 dawes Exp $
|
||||
* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/linux/drm/xf86drm.c,v 1.22 2001/05/19 00:26:45 dawes Exp $
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -98,8 +98,13 @@ typedef struct _drm_i810_init {
|
|||
I810_INIT_DMA = 0x01,
|
||||
I810_CLEANUP_DMA = 0x02
|
||||
} func;
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
int ring_map_idx;
|
||||
int buffer_map_idx;
|
||||
#else
|
||||
unsigned int mmio_offset;
|
||||
unsigned int buffers_offset;
|
||||
#endif
|
||||
int sarea_priv_offset;
|
||||
unsigned int ring_start;
|
||||
unsigned int ring_end;
|
||||
|
|
|
|||
37
linux/drm.h
37
linux/drm.h
|
|
@ -44,8 +44,27 @@
|
|||
#define DRM_IOCTL_NR(n) ((n) & 0xff)
|
||||
#endif
|
||||
|
||||
#define XFREE86_VERSION(major,minor,patch,snap) \
|
||||
((major << 16) | (minor < 8) | patch)
|
||||
|
||||
#ifndef CONFIG_XFREE86_VERSION
|
||||
#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
|
||||
#endif
|
||||
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
#define DRM_PROC_DEVICES "/proc/devices"
|
||||
#define DRM_PROC_MISC "/proc/misc"
|
||||
#define DRM_PROC_DRM "/proc/drm"
|
||||
#define DRM_DEV_DRM "/dev/drm"
|
||||
#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
|
||||
#define DRM_DEV_UID 0
|
||||
#define DRM_DEV_GID 0
|
||||
#endif
|
||||
|
||||
#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
|
||||
#define DRM_MAJOR 226
|
||||
#define DRM_MAX_MINOR 15
|
||||
#endif
|
||||
#define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
|
||||
#define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
|
||||
#define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
|
||||
|
|
@ -438,15 +457,15 @@ typedef struct drm_scatter_gather {
|
|||
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
|
||||
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
|
||||
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x47, drm_r128_fullscreen_t)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x48)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x49, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x4a, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4b, drm_r128_indices_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4c, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4d, drm_r128_depth_t)
|
||||
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4e, drm_r128_stipple_t)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
|
||||
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
|
||||
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
|
||||
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
|
||||
|
||||
/* Radeon specific ioctls */
|
||||
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
|
||||
|
|
@ -460,9 +479,9 @@ typedef struct drm_scatter_gather {
|
|||
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
|
||||
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
|
||||
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
|
||||
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4b, drm_radeon_texture_t)
|
||||
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
|
||||
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
|
||||
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
|
||||
|
||||
#ifdef CONFIG_DRM_SIS
|
||||
/* SiS specific ioctls */
|
||||
|
|
|
|||
|
|
@ -98,8 +98,13 @@ typedef struct _drm_i810_init {
|
|||
I810_INIT_DMA = 0x01,
|
||||
I810_CLEANUP_DMA = 0x02
|
||||
} func;
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
int ring_map_idx;
|
||||
int buffer_map_idx;
|
||||
#else
|
||||
unsigned int mmio_offset;
|
||||
unsigned int buffers_offset;
|
||||
#endif
|
||||
int sarea_priv_offset;
|
||||
unsigned int ring_start;
|
||||
unsigned int ring_end;
|
||||
|
|
|
|||
|
|
@ -131,7 +131,9 @@ static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
|
|||
udelay( 1 );
|
||||
}
|
||||
|
||||
#if R128_FIFO_DEBUG
|
||||
DRM_ERROR( "%s failed!\n", __FUNCTION__ );
|
||||
#endif
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
|
@ -145,7 +147,9 @@ static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
|
|||
udelay( 1 );
|
||||
}
|
||||
|
||||
#if R128_FIFO_DEBUG
|
||||
DRM_ERROR( "%s failed!\n", __FUNCTION__ );
|
||||
#endif
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
|
@ -164,7 +168,9 @@ int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
|
|||
udelay( 1 );
|
||||
}
|
||||
|
||||
#if R128_FIFO_DEBUG
|
||||
DRM_ERROR( "%s failed!\n", __FUNCTION__ );
|
||||
#endif
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -175,7 +175,11 @@ typedef struct drm_r128_init {
|
|||
R128_INIT_CCE = 0x01,
|
||||
R128_CLEANUP_CCE = 0x02
|
||||
} func;
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
int sarea_priv_offset;
|
||||
#else
|
||||
unsigned long sarea_priv_offset;
|
||||
#endif
|
||||
int is_pci;
|
||||
int cce_mode;
|
||||
int cce_secure;
|
||||
|
|
@ -189,12 +193,21 @@ typedef struct drm_r128_init {
|
|||
unsigned int depth_offset, depth_pitch;
|
||||
unsigned int span_offset;
|
||||
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
unsigned int fb_offset;
|
||||
unsigned int mmio_offset;
|
||||
unsigned int ring_offset;
|
||||
unsigned int ring_rptr_offset;
|
||||
unsigned int buffers_offset;
|
||||
unsigned int agp_textures_offset;
|
||||
#else
|
||||
unsigned long fb_offset;
|
||||
unsigned long mmio_offset;
|
||||
unsigned long ring_offset;
|
||||
unsigned long ring_rptr_offset;
|
||||
unsigned long buffers_offset;
|
||||
unsigned long agp_textures_offset;
|
||||
#endif
|
||||
} drm_r128_init_t;
|
||||
|
||||
typedef struct drm_r128_cce_stop {
|
||||
|
|
@ -202,19 +215,17 @@ typedef struct drm_r128_cce_stop {
|
|||
int idle;
|
||||
} drm_r128_cce_stop_t;
|
||||
|
||||
typedef struct drm_r128_fullscreen {
|
||||
enum {
|
||||
R128_INIT_FULLSCREEN = 0x01,
|
||||
R128_CLEANUP_FULLSCREEN = 0x02
|
||||
} func;
|
||||
} drm_r128_fullscreen_t;
|
||||
|
||||
typedef struct drm_r128_clear {
|
||||
unsigned int flags;
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
int x, y, w, h;
|
||||
#endif
|
||||
unsigned int clear_color;
|
||||
unsigned int clear_depth;
|
||||
#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
|
||||
unsigned int color_mask;
|
||||
unsigned int depth_mask;
|
||||
#endif
|
||||
} drm_r128_clear_t;
|
||||
|
||||
typedef struct drm_r128_vertex {
|
||||
|
|
@ -266,4 +277,11 @@ typedef struct drm_r128_indirect {
|
|||
int discard;
|
||||
} drm_r128_indirect_t;
|
||||
|
||||
typedef struct drm_r128_fullscreen {
|
||||
enum {
|
||||
R128_INIT_FULLSCREEN = 0x01,
|
||||
R128_CLEANUP_FULLSCREEN = 0x02
|
||||
} func;
|
||||
} drm_r128_fullscreen_t;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -910,12 +910,6 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
|
|||
*/
|
||||
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
|
||||
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
|
||||
#if defined(__alpha__)
|
||||
/* HACK! something is clobbering MEM_CNTL on Alpha! */
|
||||
DRM_ERROR( "MEM_CNTL 0x%x\n",
|
||||
RADEON_READ(0x0140) );
|
||||
RADEON_WRITE(0x0140, 0x29002901);
|
||||
#endif
|
||||
} else {
|
||||
/* Turn off PCI GART
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@ typedef struct {
|
|||
unsigned int left, right;
|
||||
} drm_sis_flip_t;
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
int sis_fb_alloc(struct inode *inode, struct file *filp, unsigned int cmd,
|
||||
unsigned long arg);
|
||||
int sis_fb_free(struct inode *inode, struct file *filp, unsigned int cmd,
|
||||
|
|
@ -30,3 +32,5 @@ int sisp_agp_free(struct inode *inode, struct file *filp, unsigned int cmd,
|
|||
unsigned long arg);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -44,8 +44,27 @@
|
|||
#define DRM_IOCTL_NR(n) ((n) & 0xff)
|
||||
#endif
|
||||
|
||||
#define XFREE86_VERSION(major,minor,patch,snap) \
|
||||
((major << 16) | (minor < 8) | patch)
|
||||
|
||||
#ifndef CONFIG_XFREE86_VERSION
|
||||
#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
|
||||
#endif
|
||||
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
#define DRM_PROC_DEVICES "/proc/devices"
|
||||
#define DRM_PROC_MISC "/proc/misc"
|
||||
#define DRM_PROC_DRM "/proc/drm"
|
||||
#define DRM_DEV_DRM "/dev/drm"
|
||||
#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
|
||||
#define DRM_DEV_UID 0
|
||||
#define DRM_DEV_GID 0
|
||||
#endif
|
||||
|
||||
#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
|
||||
#define DRM_MAJOR 226
|
||||
#define DRM_MAX_MINOR 15
|
||||
#endif
|
||||
#define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
|
||||
#define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
|
||||
#define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
|
||||
|
|
@ -438,15 +457,15 @@ typedef struct drm_scatter_gather {
|
|||
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
|
||||
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
|
||||
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x47, drm_r128_fullscreen_t)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x48)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x49, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x4a, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4b, drm_r128_indices_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4c, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4d, drm_r128_depth_t)
|
||||
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4e, drm_r128_stipple_t)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
|
||||
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
|
||||
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
|
||||
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
|
||||
|
||||
/* Radeon specific ioctls */
|
||||
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
|
||||
|
|
@ -460,9 +479,9 @@ typedef struct drm_scatter_gather {
|
|||
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
|
||||
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
|
||||
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
|
||||
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4b, drm_radeon_texture_t)
|
||||
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
|
||||
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
|
||||
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
|
||||
|
||||
#ifdef CONFIG_DRM_SIS
|
||||
/* SiS specific ioctls */
|
||||
|
|
|
|||
37
shared/drm.h
37
shared/drm.h
|
|
@ -44,8 +44,27 @@
|
|||
#define DRM_IOCTL_NR(n) ((n) & 0xff)
|
||||
#endif
|
||||
|
||||
#define XFREE86_VERSION(major,minor,patch,snap) \
|
||||
((major << 16) | (minor < 8) | patch)
|
||||
|
||||
#ifndef CONFIG_XFREE86_VERSION
|
||||
#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
|
||||
#endif
|
||||
|
||||
#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
|
||||
#define DRM_PROC_DEVICES "/proc/devices"
|
||||
#define DRM_PROC_MISC "/proc/misc"
|
||||
#define DRM_PROC_DRM "/proc/drm"
|
||||
#define DRM_DEV_DRM "/dev/drm"
|
||||
#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
|
||||
#define DRM_DEV_UID 0
|
||||
#define DRM_DEV_GID 0
|
||||
#endif
|
||||
|
||||
#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
|
||||
#define DRM_MAJOR 226
|
||||
#define DRM_MAX_MINOR 15
|
||||
#endif
|
||||
#define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */
|
||||
#define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */
|
||||
#define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */
|
||||
|
|
@ -438,15 +457,15 @@ typedef struct drm_scatter_gather {
|
|||
#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43)
|
||||
#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44)
|
||||
#define DRM_IOCTL_R128_RESET DRM_IO( 0x46)
|
||||
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x47, drm_r128_fullscreen_t)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x48)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x49, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x4a, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4b, drm_r128_indices_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4c, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4d, drm_r128_depth_t)
|
||||
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4e, drm_r128_stipple_t)
|
||||
#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47)
|
||||
#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t)
|
||||
#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t)
|
||||
#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t)
|
||||
#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t)
|
||||
#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t)
|
||||
#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t)
|
||||
#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(0x4f, drm_r128_indirect_t)
|
||||
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( 0x50, drm_r128_fullscreen_t)
|
||||
|
||||
/* Radeon specific ioctls */
|
||||
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
|
||||
|
|
@ -460,9 +479,9 @@ typedef struct drm_scatter_gather {
|
|||
#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
|
||||
#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
|
||||
#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
|
||||
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4b, drm_radeon_texture_t)
|
||||
#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
|
||||
#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
|
||||
#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
|
||||
|
||||
#ifdef CONFIG_DRM_SIS
|
||||
/* SiS specific ioctls */
|
||||
|
|
|
|||
Loading…
Reference in New Issue