radeon: VBlank rework fixups.
Fix range of frame counter registers. Use DRM_ERR() instead of Linux specific error codes in shared code. Remove duplicate register definitions and superfluous local variables.main
parent
741d1c8031
commit
d8ed021d29
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@ -512,9 +512,6 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
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#define RADEON_CRTC_CRNT_FRAME 0x0214
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#define RADEON_CRTC2_CRNT_FRAME 0x0314
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#define RADEON_CRTC_CRNT_FRAME 0x0214
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#define RADEON_CRTC2_CRNT_FRAME 0x0314
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#define RADEON_GEN_INT_CNTL 0x0040
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# define RADEON_CRTC_VBLANK_MASK (1 << 0)
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# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
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@ -49,8 +49,6 @@ static void radeon_irq_set_state(drm_device_t *dev, u32 mask, int state)
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int radeon_enable_vblank(drm_device_t *dev, int crtc)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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switch (crtc) {
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case 0:
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radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
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@ -61,7 +59,7 @@ int radeon_enable_vblank(drm_device_t *dev, int crtc)
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default:
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DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
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crtc);
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return -EINVAL;
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return DRM_ERR(EINVAL);
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}
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return 0;
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@ -69,8 +67,6 @@ int radeon_enable_vblank(drm_device_t *dev, int crtc)
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void radeon_disable_vblank(drm_device_t *dev, int crtc)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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switch (crtc) {
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case 0:
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radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
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@ -177,7 +173,7 @@ static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
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u32 radeon_get_vblank_counter(drm_device_t *dev, int crtc)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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u32 crtc_cnt_reg, current_cnt;
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u32 crtc_cnt_reg;
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if (crtc == 0)
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crtc_cnt_reg = RADEON_CRTC_CRNT_FRAME;
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@ -186,9 +182,7 @@ u32 radeon_get_vblank_counter(drm_device_t *dev, int crtc)
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else
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return 0;
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current_cnt = RADEON_READ(crtc_cnt_reg);
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return current_cnt;
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return RADEON_READ(crtc_cnt_reg);
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}
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/* Needs the lock as it touches the ring.
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@ -261,16 +255,16 @@ int radeon_driver_irq_postinstall(drm_device_t * dev)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *) dev->dev_private;
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int num_pipes = 2, ret;
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int ret;
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atomic_set(&dev_priv->swi_emitted, 0);
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DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
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ret = drm_vblank_init(dev, num_pipes);
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ret = drm_vblank_init(dev, 2);
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if (ret)
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return ret;
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dev->max_vblank_count = 0xffffffff;
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dev->max_vblank_count = 0x001fffff;
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radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
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