intel: Add support for RPLP
Add RPLP platform support and PCIIDs Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>main
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@ -666,6 +666,15 @@
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INTEL_VGA_DEVICE(0x46C2, info), \
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INTEL_VGA_DEVICE(0x46C2, info), \
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INTEL_VGA_DEVICE(0x46C3, info)
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INTEL_VGA_DEVICE(0x46C3, info)
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/* RPL-P */
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#define INTEL_RPLP_IDS(info) \
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INTEL_VGA_DEVICE(0xA720, info), \
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INTEL_VGA_DEVICE(0xA721, info), \
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INTEL_VGA_DEVICE(0xA7A0, info), \
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INTEL_VGA_DEVICE(0xA7A1, info), \
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INTEL_VGA_DEVICE(0xA7A8, info), \
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INTEL_VGA_DEVICE(0xA7A9, info)
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/* ADL-N */
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/* ADL-N */
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#define INTEL_ADLN_IDS(info) \
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#define INTEL_ADLN_IDS(info) \
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INTEL_VGA_DEVICE(0x46D0, info), \
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INTEL_VGA_DEVICE(0x46D0, info), \
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@ -35,9 +35,10 @@ static const struct pci_device {
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uint16_t gen;
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uint16_t gen;
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} pciids[] = {
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} pciids[] = {
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/* Keep ids sorted by gen; latest gen first */
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/* Keep ids sorted by gen; latest gen first */
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INTEL_RPLS_IDS(12),
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INTEL_ADLN_IDS(12),
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INTEL_ADLN_IDS(12),
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INTEL_RPLP_IDS(12),
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INTEL_ADLP_IDS(12),
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INTEL_ADLP_IDS(12),
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INTEL_RPLS_IDS(12),
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INTEL_ADLS_IDS(12),
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INTEL_ADLS_IDS(12),
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INTEL_RKL_IDS(12),
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INTEL_RKL_IDS(12),
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INTEL_DG1_IDS(12),
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INTEL_DG1_IDS(12),
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