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Revert "intel: Add support for GPU reset status query ioctl" 

This reverts commit 6335e1d28c.

No taxation without representation, in other words no userspace without kernel
stuff being in a stable location, either drm-next but I'll accept drm-intel-next
for intel specific stuff.
main
Dave Airlie 2013-11-08 16:40:18 +10:00
parent 6335e1d28c
commit da738d1ed0
3 changed files with 0 additions and 56 deletions
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17
include/drm/i915_drm.h
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@ -198,7 +198,6 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_SET_CACHEING 0x2f #define DRM_I915_GEM_SET_CACHEING 0x2f
#define DRM_I915_GEM_GET_CACHEING 0x30 #define DRM_I915_GEM_GET_CACHEING 0x30
#define DRM_I915_REG_READ 0x31 #define DRM_I915_REG_READ 0x31
#define DRM_I915_GET_RESET_STATS 0x32
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@ -248,7 +247,6 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
/* Allow drivers to submit batchbuffers directly to hardware, relying /* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware. * on the security mechanisms provided by hardware.
@ -945,19 +943,4 @@ struct drm_i915_reg_read {
__u64 offset; __u64 offset;
__u64 val; /* Return value */ __u64 val; /* Return value */
}; };
struct drm_i915_reset_stats {
__u32 ctx_id;
__u32 flags;
/* For all contexts */
__u32 reset_count;
/* For this context */
__u32 batch_active;
__u32 batch_pending;
__u32 pad;
};
#endif /* _I915_DRM_H_ */ #endif /* _I915_DRM_H_ */

5
intel/intel_bufmgr.h
View File

@ -248,11 +248,6 @@ int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
uint32_t offset, uint32_t offset,
uint64_t *result); uint64_t *result);
int drm_intel_get_reset_stats(drm_intel_context *ctx,
uint32_t *reset_count,
uint32_t *active,
uint32_t *pending);
/** @{ Compatibility defines to keep old code building despite the symbol rename /** @{ Compatibility defines to keep old code building despite the symbol rename
* from dri_* to drm_intel_* * from dri_* to drm_intel_*
*/ */

34
intel/intel_bufmgr_gem.c
View File

@ -3020,40 +3020,6 @@ drm_intel_gem_context_destroy(drm_intel_context *ctx)
free(ctx); free(ctx);
} }
int
drm_intel_get_reset_stats(drm_intel_context *ctx,
uint32_t *reset_count,
uint32_t *active,
uint32_t *pending)
{
drm_intel_bufmgr_gem *bufmgr_gem;
struct drm_i915_reset_stats stats;
int ret;
if (ctx == NULL)
return -EINVAL;
VG_CLEAR(stats);
bufmgr_gem = (drm_intel_bufmgr_gem *)ctx->bufmgr;
stats.ctx_id = ctx->ctx_id;
ret = drmIoctl(bufmgr_gem->fd,
DRM_IOCTL_I915_GET_RESET_STATS,
&stats);
if (ret == 0) {
if (reset_count != NULL)
*reset_count = stats.reset_count;
if (active != NULL)
*active = stats.batch_active;
if (pending != NULL)
*pending = stats.batch_pending;
}
return ret;
}
int int
drm_intel_reg_read(drm_intel_bufmgr *bufmgr, drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
uint32_t offset, uint32_t offset,