Initial checkin of vblank rework. Code attempts to reduce the number
of vblank interrupt in order to save power.main
Jesse Barnes
parent
280083d4a2
commit
db689c7b95
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@ -627,8 +627,9 @@ struct drm_driver {
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int (*kernel_context_switch) (struct drm_device * dev, int old,
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int new);
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void (*kernel_context_switch_unlock) (struct drm_device * dev);
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int (*vblank_wait) (struct drm_device * dev, unsigned int *sequence);
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int (*vblank_wait2) (struct drm_device * dev, unsigned int *sequence);
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u32 (*get_vblank_counter) (struct drm_device *dev, int crtc);
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void (*enable_vblank) (struct drm_device *dev, int crtc);
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void (*disable_vblank) (struct drm_device *dev, int crtc);
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int (*dri_library_name) (struct drm_device * dev, char * buf);
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/**
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@ -783,12 +784,13 @@ typedef struct drm_device {
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/*@{ */
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wait_queue_head_t vbl_queue; /**< VBLANK wait queue */
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atomic_t vbl_received;
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atomic_t vbl_received2; /**< number of secondary VBLANK interrupts */
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atomic_t *vblank_count; /**< number of VBLANK interrupts (driver must alloc the right number of counters) */
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spinlock_t vbl_lock;
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struct list_head vbl_sigs; /**< signal list to send on VBLANK */
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struct list_head vbl_sigs2; /**< signals to send on secondary VBLANK */
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unsigned int vbl_pending;
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atomic_t *vbl_pending;
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u32 *last_vblank; /* protected by dev->vbl_lock */
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unsigned long max_vblank_count; /**< size of vblank counter register */
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spinlock_t tasklet_lock; /**< For drm_locked_tasklet */
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void (*locked_tasklet_func)(struct drm_device *dev);
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@ -221,6 +221,44 @@ int drm_control(struct inode *inode, struct file *filp,
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}
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}
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static void drm_vblank_get(drm_device_t *dev, int crtc)
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{
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unsigned long irqflags;
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u32 cur_vblank, diff;
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if (atomic_add_return(1, &dev->vbl_pending[crtc]) != 1)
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return;
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/*
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* Interrupts were disabled prior to this call, so deal with counter
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* wrap if needed.
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* NOTE! It's possible we lost a full dev->max_vblank_count events
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* here if the register is small or we had vblank interrupts off for
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* a long time.
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*/
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cur_vblank = dev->driver->get_vblank_counter(dev, crtc);
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spin_lock_irqsave(&dev->vbl_lock, irqflags);
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if (cur_vblank < dev->last_vblank[crtc]) {
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diff = dev->max_vblank_count -
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dev->last_vblank[crtc];
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diff += cur_vblank;
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} else {
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diff = cur_vblank - last_vblank;
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}
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dev->last_vblank[crtc] = cur_vblank;
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spin_lock_irqrestore(&dev->vbl_lock, irqflags);
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atomic_add(diff, &dev->vblank_count[crtc]);
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dev->driver->enable_vblank(dev, crtc);
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}
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static void drm_vblank_put(drm_device_t *dev, int crtc)
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{
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if (atomic_dec_and_test(&dev->vbl_pending[crtc]))
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dev->driver->disable_vblank(dev, crtc);
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}
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/**
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* Wait for VBLANK.
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*
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@ -248,7 +286,7 @@ int drm_wait_vblank(DRM_IOCTL_ARGS)
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drm_wait_vblank_t vblwait;
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struct timeval now;
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int ret = 0;
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unsigned int flags, seq;
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unsigned int flags, seq, crtc;
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if ((!dev->irq) || (!dev->irq_enabled))
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return -EINVAL;
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@ -265,13 +303,14 @@ int drm_wait_vblank(DRM_IOCTL_ARGS)
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}
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flags = vblwait.request.type & _DRM_VBLANK_FLAGS_MASK;
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crtc = flags & _DRM_VBLANK_SECONDARY ? 1 : 0;
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if (!drm_core_check_feature(dev, (flags & _DRM_VBLANK_SECONDARY) ?
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DRIVER_IRQ_VBL2 : DRIVER_IRQ_VBL))
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return -EINVAL;
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seq = atomic_read((flags & _DRM_VBLANK_SECONDARY) ? &dev->vbl_received2
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: &dev->vbl_received);
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drm_vblank_get(dev, crtc);
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seq = atomic_read(&dev->vblank_count[crtc]);
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switch (vblwait.request.type & _DRM_VBLANK_TYPES_MASK) {
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case _DRM_VBLANK_RELATIVE:
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@ -307,22 +346,23 @@ int drm_wait_vblank(DRM_IOCTL_ARGS)
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spin_unlock_irqrestore(&dev->vbl_lock,
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irqflags);
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vblwait.reply.sequence = seq;
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drm_vblank_put(dev, crtc);
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goto done;
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}
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}
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if (dev->vbl_pending >= 100) {
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if (atomic_read(&dev->vbl_pending[crtc]) >= 100) {
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spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
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drm_vblank_put(dev, crtc);
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return -EBUSY;
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}
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dev->vbl_pending++;
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spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
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if (!
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(vbl_sig =
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drm_alloc(sizeof(drm_vbl_sig_t), DRM_MEM_DRIVER))) {
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drm_vblank_put(dev, crtc);
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return -ENOMEM;
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}
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@ -340,14 +380,12 @@ int drm_wait_vblank(DRM_IOCTL_ARGS)
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vblwait.reply.sequence = seq;
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} else {
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if (flags & _DRM_VBLANK_SECONDARY) {
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if (dev->driver->vblank_wait2)
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ret = dev->driver->vblank_wait2(dev, &vblwait.request.sequence);
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} else if (dev->driver->vblank_wait)
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ret =
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dev->driver->vblank_wait(dev,
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&vblwait.request.sequence);
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unsigned long cur_vblank;
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DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
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(((cur_vblank = atomic_read(&dev->vblank_count[crtc]))
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- seq) <= (1 << 23)));
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drm_vblank_put(dev, crtc);
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do_gettimeofday(&now);
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vblwait.reply.tval_sec = now.tv_sec;
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vblwait.reply.tval_usec = now.tv_usec;
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@ -379,8 +417,7 @@ void drm_vbl_send_signals(drm_device_t * dev)
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for (i = 0; i < 2; i++) {
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drm_vbl_sig_t *vbl_sig, *tmp;
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struct list_head *vbl_sigs = i ? &dev->vbl_sigs2 : &dev->vbl_sigs;
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unsigned int vbl_seq = atomic_read(i ? &dev->vbl_received2 :
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&dev->vbl_received);
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unsigned int vbl_seq = atomic_read(&dev->vblank_count[i]);
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list_for_each_entry_safe(vbl_sig, tmp, vbl_sigs, head) {
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if ((vbl_seq - vbl_sig->sequence) <= (1 << 23)) {
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@ -393,7 +430,7 @@ void drm_vbl_send_signals(drm_device_t * dev)
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drm_free(vbl_sig, sizeof(*vbl_sig),
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DRM_MEM_DRIVER);
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dev->vbl_pending--;
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drm_vblank_put(dev, i);
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}
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}
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}
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@ -83,8 +83,9 @@ static struct drm_driver driver = {
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.lastclose = i915_driver_lastclose,
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.preclose = i915_driver_preclose,
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.device_is_agp = i915_driver_device_is_agp,
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.vblank_wait = i915_driver_vblank_wait,
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.vblank_wait2 = i915_driver_vblank_wait2,
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.get_vblank_counter = i915_get_vblank_counter,
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.enable_vblank = i915_enable_vblank,
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.disable_vblank = i915_disable_vblank,
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.irq_preinstall = i915_driver_irq_preinstall,
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.irq_postinstall = i915_driver_irq_postinstall,
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.irq_uninstall = i915_driver_irq_uninstall,
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@ -833,6 +833,20 @@ static int i915_setparam(DRM_IOCTL_ARGS)
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case I915_SETPARAM_ALLOW_BATCHBUFFER:
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dev_priv->allow_batchbuffer = param.value;
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break;
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case I915_SETPARAM_PREMODESET:
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if (param.value > 1) {
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DRM_ERROR("bad crtc\n");
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return -EINVAL;
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}
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i915_premodeset(dev, param.value);
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break;
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case I915_SETPARAM_POSTMODESET:
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if (param.value > 1) {
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DRM_ERROR("bad crtc\n");
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return -EINVAL;
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}
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i915_postmodeset(dev, param.value);
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break;
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default:
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DRM_ERROR("unknown parameter %d\n", param.param);
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return DRM_ERR(EINVAL);
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@ -235,6 +235,8 @@ typedef struct drm_i915_getparam {
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#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
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#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
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#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
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#define I915_SETPARAM_PREMODESET 4
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#define I915_SETPARAM_POSTMODESET 5
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typedef struct drm_i915_setparam {
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int param;
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@ -132,6 +132,8 @@ typedef struct drm_i915_private {
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spinlock_t swaps_lock;
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drm_i915_vbl_swap_t vbl_swaps;
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unsigned int swaps_pending;
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unsigned long vblank_offset[2];
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unsigned long vblank_premodeset[2];
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} drm_i915_private_t;
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enum intel_chip_family {
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@ -161,8 +163,6 @@ extern int i915_driver_firstopen(struct drm_device *dev);
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extern int i915_irq_emit(DRM_IOCTL_ARGS);
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extern int i915_irq_wait(DRM_IOCTL_ARGS);
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extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
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extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence);
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extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
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extern void i915_driver_irq_preinstall(drm_device_t * dev);
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extern void i915_driver_irq_postinstall(drm_device_t * dev);
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@ -173,6 +173,11 @@ extern int i915_emit_irq(drm_device_t * dev);
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extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
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extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
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extern int i915_vblank_swap(DRM_IOCTL_ARGS);
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extern void i915_enable_vblank(drm_device_t *dev, int crtc);
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extern void i915_disable_vblank(drm_device_t *dev, int crtc);
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extern u32 i915_get_vblank_counter(drm_device_t *dev, int crtc);
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extern void i915_premodeset(drm_device_t *dev, int crtc);
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extern void i915_postmodeset(drm_device_t *dev, int crtc);
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/* i915_mem.c */
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extern int i915_mem_alloc(DRM_IOCTL_ARGS);
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@ -271,6 +276,36 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
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#define I915REG_PIPEASTAT 0x70024
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#define I915REG_PIPEBSTAT 0x71024
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/*
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* The two pipe frame counter registers are not synchronized, so
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* reading a stable value is somewhat tricky. The following code
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* should work:
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*
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* do {
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* high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
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* PIPE_FRAME_HIGH_SHIFT;
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* low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
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* PIPE_FRAME_LOW_SHIFT);
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* high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
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* PIPE_FRAME_HIGH_SHIFT);
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* } while (high1 != high2);
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* frame = (high1 << 8) | low1;
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*/
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#define PIPEAFRAMEHIGH 0x70040
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#define PIPEBFRAMEHIGH 0x71040
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#define PIPE_FRAME_HIGH_MASK 0x0000ffff
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#define PIPE_FRAME_HIGH_SHIFT 0
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#define PIPEAFRAMEPIXEL 0x70044
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#define PIPEBFRAMEPIXEL 0x71044
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#define PIPE_FRAME_LOW_MASK 0xff000000
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#define PIPE_FRAME_LOW_SHIFT 24
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/*
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* Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register
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* and is 24 bits wide.
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*/
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#define PIPE_PIXEL_MASK 0x00ffffff
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#define PIPE_PIXEL_SHIFT 0
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#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
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#define I915_VBLANK_CLEAR (1UL<<1)
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@ -92,8 +92,8 @@ static void i915_vblank_tasklet(drm_device_t *dev)
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unsigned long irqflags;
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struct list_head *list, *tmp, hits, *hit;
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int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
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unsigned counter[2] = { atomic_read(&dev->vbl_received),
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atomic_read(&dev->vbl_received2) };
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unsigned counter[2] = { atomic_read(&dev->vblank_count[0]),
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atomic_read(&dev->vblank_count[1]) };
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drm_drawable_info_t *drw;
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drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
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u32 cpp = dev_priv->cpp, offsets[3];
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@ -313,14 +313,14 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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(DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
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== (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
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if (temp & VSYNC_PIPEA_FLAG)
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atomic_inc(&dev->vbl_received);
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atomic_inc(&dev->vblank_count[0]);
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if (temp & VSYNC_PIPEB_FLAG)
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atomic_inc(&dev->vbl_received2);
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atomic_inc(&dev->vblank_count[1]);
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} else if (((temp & VSYNC_PIPEA_FLAG) &&
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(vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
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((temp & VSYNC_PIPEB_FLAG) &&
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(vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
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atomic_inc(&dev->vbl_received);
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atomic_inc(&dev->vblank_count[0]);
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DRM_WAKEUP(&dev->vbl_queue);
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drm_vbl_send_signals(dev);
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@ -410,37 +410,6 @@ static int i915_wait_irq(drm_device_t * dev, int irq_nr)
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return ret;
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}
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static int i915_driver_vblank_do_wait(drm_device_t *dev, unsigned int *sequence,
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atomic_t *counter)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned int cur_vblank;
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int ret = 0;
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if (!dev_priv) {
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DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
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return DRM_ERR(EINVAL);
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}
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DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
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(((cur_vblank = atomic_read(counter))
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- *sequence) <= (1<<23)));
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*sequence = cur_vblank;
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return ret;
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}
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int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
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{
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return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
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}
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int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
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{
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return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
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}
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/* Needs the lock as it touches the ring.
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*/
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int i915_irq_emit(DRM_IOCTL_ARGS)
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@ -489,15 +458,99 @@ int i915_irq_wait(DRM_IOCTL_ARGS)
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return i915_wait_irq(dev, irqwait.irq_seq);
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}
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void i915_enable_vblank(drm_device_t *dev, int crtc)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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switch (crtc) {
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case 0:
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dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
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break;
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case 1:
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dev_priv->irq_enable_reg |= VSYNC_PIPEB_FLAG;
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break;
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default:
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DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
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crtc);
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break;
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}
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I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
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}
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void i915_disable_vblank(drm_device_t *dev, int crtc)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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switch (crtc) {
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case 0:
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dev_priv->irq_enable_reg &= ~VSYNC_PIPEA_FLAG;
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break;
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case 1:
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dev_priv->irq_enable_reg &= ~VSYNC_PIPEB_FLAG;
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break;
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default:
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DRM_ERROR("tried to disable vblank on non-existent crtc %d\n",
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crtc);
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break;
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}
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I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
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}
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static u32 i915_vblank_counter(drm_device_t *dev, int crtc)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long high_frame = crtc ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
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unsigned long low_frame = crtc ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
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u32 high1, high2, low, count;
|
||||
|
||||
/*
|
||||
* High & low register fields aren't synchronized, so make sure
|
||||
* we get a low value that's stable across two reads of the high
|
||||
* register.
|
||||
*/
|
||||
do {
|
||||
high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
||||
PIPE_FRAME_HIGH_SHIFT);
|
||||
low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
|
||||
PIPE_FRAME_LOW_SHIFT);
|
||||
high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
|
||||
PIPE_FRAME_HIGH_SHIFT);
|
||||
} while (high1 != high2);
|
||||
|
||||
count = (high1 << 8) | low;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
u32 i915_get_vblank_counter(drm_device_t *dev, int crtc)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
return i915_vblank_counter(dev, crtc) + dev_priv->vblank_offset[crtc];
|
||||
}
|
||||
|
||||
void i915_premodeset(drm_device_t *dev, int crtc)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
|
||||
dev_priv->vblank_premodeset[crtc] = i915_vblank_counter(dev, crtc);
|
||||
}
|
||||
|
||||
void i915_postmodeset(drm_device_t *dev, int crtc)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = dev->dev_private;
|
||||
u32 new;
|
||||
|
||||
new = i915_vblank_counter(dev, crtc);
|
||||
dev_priv->vblank_offset[crtc] = dev_priv->vblank_premodeset[crtc] - new;
|
||||
}
|
||||
|
||||
static void i915_enable_interrupt (drm_device_t *dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
|
||||
dev_priv->irq_enable_reg = USER_INT_FLAG;
|
||||
if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
|
||||
dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
|
||||
if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
|
||||
dev_priv->irq_enable_reg |= VSYNC_PIPEB_FLAG;
|
||||
dev_priv->irq_enable_reg |= USER_INT_FLAG;
|
||||
|
||||
I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
|
||||
dev_priv->irq_enabled = 1;
|
||||
|
|
@ -607,7 +660,7 @@ int i915_vblank_swap(DRM_IOCTL_ARGS)
|
|||
|
||||
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
|
||||
|
||||
curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received);
|
||||
curseq = atomic_read(&dev->vblank_count[pipe]);
|
||||
|
||||
if (seqtype == _DRM_VBLANK_RELATIVE)
|
||||
swap.sequence += curseq;
|
||||
|
|
@ -714,6 +767,7 @@ void i915_driver_irq_preinstall(drm_device_t * dev)
|
|||
void i915_driver_irq_postinstall(drm_device_t * dev)
|
||||
{
|
||||
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
||||
int i;
|
||||
|
||||
spin_lock_init(&dev_priv->swaps_lock);
|
||||
INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
|
||||
|
|
@ -721,6 +775,34 @@ void i915_driver_irq_postinstall(drm_device_t * dev)
|
|||
|
||||
dev_priv->user_irq_lock = SPIN_LOCK_UNLOCKED;
|
||||
dev_priv->user_irq_refcount = 0;
|
||||
dev_priv->irq_enable_reg = 0;
|
||||
dev->vblank_count = kmalloc(sizeof(atomic_t) * 2, GFP_KERNEL);
|
||||
if (!dev->vblank_count) {
|
||||
DRM_ERROR("out of memory\n");
|
||||
return;
|
||||
}
|
||||
dev->vbl_pending = kmalloc(sizeof(atomic_t) * 2, GFP_KERNEL);
|
||||
if (!dev->vbl_pending) {
|
||||
DRM_ERROR("out of memory\n");
|
||||
kfree(dev->vblank_count);
|
||||
return;
|
||||
}
|
||||
dev->last_vblank = kmalloc(sizeof(atomic_t) * 2, GFP_KERNEL);
|
||||
if (!dev->last_vblank) {
|
||||
DRM_ERROR("out of memory\n");
|
||||
kfree(dev->vblank_count);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Zero per-crtc vblank stuff */
|
||||
for (i = 0; i < 2; i++) {
|
||||
atomic_set(&dev->vbl_pending[i], 0);
|
||||
atomic_set(&dev->vblank_count[i], 0);
|
||||
dev->last_vblank[i] = 0;
|
||||
dev_priv->vblank_offset[i] = 0;
|
||||
}
|
||||
|
||||
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
|
||||
|
||||
i915_enable_interrupt(dev);
|
||||
DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
|
||||
|
|
|
|||
|
|
@ -299,6 +299,9 @@ typedef struct drm_radeon_private {
|
|||
|
||||
u32 scratch_ages[5];
|
||||
|
||||
unsigned int crtc_last_cnt;
|
||||
unsigned int crtc2_last_cnt;
|
||||
|
||||
/* starting from here on, data is preserved accross an open */
|
||||
uint32_t flags; /* see radeon_chip_flags */
|
||||
|
||||
|
|
@ -364,9 +367,9 @@ extern int radeon_irq_wait(DRM_IOCTL_ARGS);
|
|||
|
||||
extern void radeon_do_release(drm_device_t * dev);
|
||||
extern int radeon_driver_vblank_wait(drm_device_t * dev,
|
||||
unsigned int *sequence);
|
||||
unsigned int *sequence, int relative);
|
||||
extern int radeon_driver_vblank_wait2(drm_device_t * dev,
|
||||
unsigned int *sequence);
|
||||
unsigned int *sequence, int relative);
|
||||
extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
|
||||
extern void radeon_driver_irq_preinstall(drm_device_t * dev);
|
||||
extern void radeon_driver_irq_postinstall(drm_device_t * dev);
|
||||
|
|
@ -507,6 +510,9 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
|
|||
? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
|
||||
: RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
|
||||
|
||||
#define RADEON_CRTC_CRNT_FRAME 0x0214
|
||||
#define RADEON_CRTC2_CRNT_FRAME 0x0314
|
||||
|
||||
#define RADEON_GEN_INT_CNTL 0x0040
|
||||
# define RADEON_CRTC_VBLANK_MASK (1 << 0)
|
||||
# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
|
||||
|
|
|
|||
|
|
@ -35,6 +35,18 @@
|
|||
#include "radeon_drm.h"
|
||||
#include "radeon_drv.h"
|
||||
|
||||
static void radeon_irq_set_state(drm_device_t *dev, u32 mask, int state)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
|
||||
|
||||
if (state)
|
||||
dev_priv->irq_enable_reg |= mask;
|
||||
else
|
||||
dev_priv->irq_enable_reg &= ~mask;
|
||||
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
|
||||
}
|
||||
|
||||
static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
|
||||
u32 mask)
|
||||
{
|
||||
|
|
@ -141,14 +153,17 @@ static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
|
|||
}
|
||||
|
||||
int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
|
||||
int crtc)
|
||||
int crtc, int relative)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv =
|
||||
(drm_radeon_private_t *) dev->dev_private;
|
||||
unsigned int cur_vblank;
|
||||
unsigned int cur_vblank, diff, irqflags, current_cnt;
|
||||
int ret = 0;
|
||||
int ack = 0;
|
||||
atomic_t *counter;
|
||||
unsigned int *last_cnt;
|
||||
int crtc_cnt_reg;
|
||||
|
||||
if (!dev_priv) {
|
||||
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
|
||||
return DRM_ERR(EINVAL);
|
||||
|
|
@ -156,10 +171,14 @@ int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
|
|||
|
||||
if (crtc == DRM_RADEON_VBLANK_CRTC1) {
|
||||
counter = &dev->vbl_received;
|
||||
ack |= RADEON_CRTC_VBLANK_STAT;
|
||||
ack = RADEON_CRTC_VBLANK_STAT;
|
||||
last_cnt = &dev_priv->crtc_last_cnt;
|
||||
crtc_cnt_reg = RADEON_CRTC_CRNT_FRAME;
|
||||
} else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
|
||||
counter = &dev->vbl_received2;
|
||||
ack |= RADEON_CRTC2_VBLANK_STAT;
|
||||
ack = RADEON_CRTC2_VBLANK_STAT;
|
||||
last_cnt = &dev_priv->crtc2_last_cnt;
|
||||
crtc_cnt_reg = RADEON_CRTC2_CRNT_FRAME;
|
||||
} else
|
||||
return DRM_ERR(EINVAL);
|
||||
|
||||
|
|
@ -167,27 +186,46 @@ int radeon_driver_vblank_do_wait(drm_device_t * dev, unsigned int *sequence,
|
|||
|
||||
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
|
||||
|
||||
if (!relative) {
|
||||
/*
|
||||
* Assume we haven't missed more than several hours of vblank
|
||||
* events, or that it won't matter if they're not accounted
|
||||
* for in the master counter.
|
||||
*/
|
||||
spin_lock_irqsave(&dev->vbl_lock, irqflags);
|
||||
current_cnt = RADEON_READ(crtc_cnt_reg);
|
||||
if (current_cnt < *last_cnt) {
|
||||
current_cnt += (1 << 21) - *last_cnt;
|
||||
*last_cnt = 0;
|
||||
}
|
||||
diff = current_cnt - *last_cnt;
|
||||
*last_cnt = RADEON_READ(crtc_cnt_reg);
|
||||
spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
|
||||
atomic_add(diff, counter);
|
||||
}
|
||||
|
||||
/* Assume that the user has missed the current sequence number
|
||||
* by about a day rather than she wants to wait for years
|
||||
* using vertical blanks...
|
||||
*/
|
||||
radeon_irq_set_state(dev, ack, 1);
|
||||
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
|
||||
(((cur_vblank = atomic_read(counter))
|
||||
- *sequence) <= (1 << 23)));
|
||||
|
||||
radeon_irq_set_state(dev, ack, 0);
|
||||
*sequence = cur_vblank;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
|
||||
int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence, int relative)
|
||||
{
|
||||
return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
|
||||
return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1, relative);
|
||||
}
|
||||
|
||||
int radeon_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence)
|
||||
int radeon_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence, int relative)
|
||||
{
|
||||
return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
|
||||
return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2, relative);
|
||||
}
|
||||
|
||||
/* Needs the lock as it touches the ring.
|
||||
|
|
@ -238,20 +276,7 @@ int radeon_irq_wait(DRM_IOCTL_ARGS)
|
|||
return radeon_wait_irq(dev, irqwait.irq_seq);
|
||||
}
|
||||
|
||||
static void radeon_enable_interrupt(drm_device_t *dev)
|
||||
{
|
||||
drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
|
||||
|
||||
dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
|
||||
if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
|
||||
dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
|
||||
|
||||
if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
|
||||
dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
|
||||
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
|
||||
dev_priv->irq_enabled = 1;
|
||||
}
|
||||
|
||||
/* drm_dma.h hooks
|
||||
*/
|
||||
|
|
@ -265,7 +290,8 @@ void radeon_driver_irq_preinstall(drm_device_t * dev)
|
|||
|
||||
/* Clear bits if they're already high */
|
||||
radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
|
||||
RADEON_CRTC_VBLANK_STAT));
|
||||
RADEON_CRTC_VBLANK_STAT |
|
||||
RADEON_CRTC2_VBLANK_STAT));
|
||||
}
|
||||
|
||||
void radeon_driver_irq_postinstall(drm_device_t * dev)
|
||||
|
|
@ -276,7 +302,7 @@ void radeon_driver_irq_postinstall(drm_device_t * dev)
|
|||
atomic_set(&dev_priv->swi_emitted, 0);
|
||||
DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
|
||||
|
||||
radeon_enable_interrupt(dev);
|
||||
radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
|
||||
}
|
||||
|
||||
void radeon_driver_irq_uninstall(drm_device_t * dev)
|
||||
|
|
@ -318,6 +344,5 @@ int radeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
|
|||
return DRM_ERR(EINVAL);
|
||||
}
|
||||
dev_priv->vblank_crtc = (unsigned int)value;
|
||||
radeon_enable_interrupt(dev);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue