diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 34904e38..c0f42e81 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -69,9 +69,9 @@ static int amdgpu_bo_create(amdgpu_device_handle dev, return 0; } -int amdgpu_bo_alloc(amdgpu_device_handle dev, - struct amdgpu_bo_alloc_request *alloc_buffer, - amdgpu_bo_handle *buf_handle) +drm_public int amdgpu_bo_alloc(amdgpu_device_handle dev, + struct amdgpu_bo_alloc_request *alloc_buffer, + amdgpu_bo_handle *buf_handle) { union drm_amdgpu_gem_create args; int r; @@ -107,8 +107,8 @@ out: return r; } -int amdgpu_bo_set_metadata(amdgpu_bo_handle bo, - struct amdgpu_bo_metadata *info) +drm_public int amdgpu_bo_set_metadata(amdgpu_bo_handle bo, + struct amdgpu_bo_metadata *info) { struct drm_amdgpu_gem_metadata args = {}; @@ -130,8 +130,8 @@ int amdgpu_bo_set_metadata(amdgpu_bo_handle bo, &args, sizeof(args)); } -int amdgpu_bo_query_info(amdgpu_bo_handle bo, - struct amdgpu_bo_info *info) +drm_public int amdgpu_bo_query_info(amdgpu_bo_handle bo, + struct amdgpu_bo_info *info) { struct drm_amdgpu_gem_metadata metadata = {}; struct drm_amdgpu_gem_create_in bo_info = {}; @@ -227,9 +227,9 @@ static int amdgpu_bo_export_flink(amdgpu_bo_handle bo) return r; } -int amdgpu_bo_export(amdgpu_bo_handle bo, - enum amdgpu_bo_handle_type type, - uint32_t *shared_handle) +drm_public int amdgpu_bo_export(amdgpu_bo_handle bo, + enum amdgpu_bo_handle_type type, + uint32_t *shared_handle) { int r; @@ -255,9 +255,9 @@ int amdgpu_bo_export(amdgpu_bo_handle bo, return -EINVAL; } -int amdgpu_bo_import(amdgpu_device_handle dev, - enum amdgpu_bo_handle_type type, - uint32_t shared_handle, +drm_public int amdgpu_bo_import(amdgpu_device_handle dev, + enum amdgpu_bo_handle_type type, + uint32_t shared_handle, struct amdgpu_bo_import_result *output) { struct drm_gem_open open_arg = {}; @@ -401,7 +401,7 @@ unlock: return r; } -int amdgpu_bo_free(amdgpu_bo_handle buf_handle) +drm_public int amdgpu_bo_free(amdgpu_bo_handle buf_handle) { struct amdgpu_device *dev; struct amdgpu_bo *bo = buf_handle; @@ -433,12 +433,12 @@ int amdgpu_bo_free(amdgpu_bo_handle buf_handle) return 0; } -void amdgpu_bo_inc_ref(amdgpu_bo_handle bo) +drm_public void amdgpu_bo_inc_ref(amdgpu_bo_handle bo) { atomic_inc(&bo->refcount); } -int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) +drm_public int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) { union drm_amdgpu_gem_mmap args; void *ptr; @@ -486,7 +486,7 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) return 0; } -int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo) +drm_public int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo) { int r; @@ -512,7 +512,7 @@ int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo) return r; } -int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, +drm_public int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, struct amdgpu_buffer_size_alignments *info) { info->size_local = dev->dev_info.pte_fragment_size; @@ -520,8 +520,8 @@ int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev, return 0; } -int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, - uint64_t timeout_ns, +drm_public int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, + uint64_t timeout_ns, bool *busy) { union drm_amdgpu_gem_wait_idle args; @@ -543,11 +543,11 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, } } -int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, - void *cpu, - uint64_t size, - amdgpu_bo_handle *buf_handle, - uint64_t *offset_in_bo) +drm_public int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, + void *cpu, + uint64_t size, + amdgpu_bo_handle *buf_handle, + uint64_t *offset_in_bo) { struct amdgpu_bo *bo; uint32_t i; @@ -585,10 +585,10 @@ int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, return r; } -int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, - void *cpu, - uint64_t size, - amdgpu_bo_handle *buf_handle) +drm_public int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, + void *cpu, + uint64_t size, + amdgpu_bo_handle *buf_handle) { int r; struct drm_amdgpu_gem_userptr args; @@ -618,11 +618,11 @@ out: return r; } -int amdgpu_bo_list_create(amdgpu_device_handle dev, - uint32_t number_of_resources, - amdgpu_bo_handle *resources, - uint8_t *resource_prios, - amdgpu_bo_list_handle *result) +drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev, + uint32_t number_of_resources, + amdgpu_bo_handle *resources, + uint8_t *resource_prios, + amdgpu_bo_list_handle *result) { struct drm_amdgpu_bo_list_entry *list; union drm_amdgpu_bo_list args; @@ -673,7 +673,7 @@ int amdgpu_bo_list_create(amdgpu_device_handle dev, return 0; } -int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list) +drm_public int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list) { union drm_amdgpu_bo_list args; int r; @@ -691,10 +691,10 @@ int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list) return r; } -int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, - uint32_t number_of_resources, - amdgpu_bo_handle *resources, - uint8_t *resource_prios) +drm_public int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, + uint32_t number_of_resources, + amdgpu_bo_handle *resources, + uint8_t *resource_prios) { struct drm_amdgpu_bo_list_entry *list; union drm_amdgpu_bo_list args; @@ -732,12 +732,12 @@ int amdgpu_bo_list_update(amdgpu_bo_list_handle handle, return r; } -int amdgpu_bo_va_op(amdgpu_bo_handle bo, - uint64_t offset, - uint64_t size, - uint64_t addr, - uint64_t flags, - uint32_t ops) +drm_public int amdgpu_bo_va_op(amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops) { amdgpu_device_handle dev = bo->dev; @@ -749,13 +749,13 @@ int amdgpu_bo_va_op(amdgpu_bo_handle bo, AMDGPU_VM_PAGE_EXECUTABLE, ops); } -int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, - amdgpu_bo_handle bo, - uint64_t offset, - uint64_t size, - uint64_t addr, - uint64_t flags, - uint32_t ops) +drm_public int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, + amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops) { struct drm_amdgpu_gem_va va; int r; diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 3c9be6c2..3b8231aa 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -48,8 +48,9 @@ static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem); * * \return 0 on success otherwise POSIX Error code */ -int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, uint32_t priority, - amdgpu_context_handle *context) +drm_public int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, + uint32_t priority, + amdgpu_context_handle *context) { struct amdgpu_context *gpu_context; union drm_amdgpu_ctx args; @@ -93,8 +94,8 @@ error: return r; } -int amdgpu_cs_ctx_create(amdgpu_device_handle dev, - amdgpu_context_handle *context) +drm_public int amdgpu_cs_ctx_create(amdgpu_device_handle dev, + amdgpu_context_handle *context) { return amdgpu_cs_ctx_create2(dev, AMDGPU_CTX_PRIORITY_NORMAL, context); } @@ -107,7 +108,7 @@ int amdgpu_cs_ctx_create(amdgpu_device_handle dev, * * \return 0 on success otherwise POSIX Error code */ -int amdgpu_cs_ctx_free(amdgpu_context_handle context) +drm_public int amdgpu_cs_ctx_free(amdgpu_context_handle context) { union drm_amdgpu_ctx args; int i, j, k; @@ -141,8 +142,8 @@ int amdgpu_cs_ctx_free(amdgpu_context_handle context) return r; } -int amdgpu_cs_query_reset_state(amdgpu_context_handle context, - uint32_t *state, uint32_t *hangs) +drm_public int amdgpu_cs_query_reset_state(amdgpu_context_handle context, + uint32_t *state, uint32_t *hangs) { union drm_amdgpu_ctx args; int r; @@ -323,10 +324,10 @@ error_unlock: return r; } -int amdgpu_cs_submit(amdgpu_context_handle context, - uint64_t flags, - struct amdgpu_cs_request *ibs_request, - uint32_t number_of_requests) +drm_public int amdgpu_cs_submit(amdgpu_context_handle context, + uint64_t flags, + struct amdgpu_cs_request *ibs_request, + uint32_t number_of_requests) { uint32_t i; int r; @@ -407,10 +408,10 @@ static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context, return 0; } -int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, - uint64_t timeout_ns, - uint64_t flags, - uint32_t *expired) +drm_public int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, + uint64_t timeout_ns, + uint64_t flags, + uint32_t *expired) { bool busy = true; int r; @@ -478,12 +479,12 @@ static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences, return 0; } -int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, - uint32_t fence_count, - bool wait_all, - uint64_t timeout_ns, - uint32_t *status, - uint32_t *first) +drm_public int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, + uint32_t fence_count, + bool wait_all, + uint64_t timeout_ns, + uint32_t *status, + uint32_t *first) { uint32_t i; @@ -506,7 +507,7 @@ int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences, timeout_ns, status, first); } -int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) +drm_public int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) { struct amdgpu_semaphore *gpu_semaphore; @@ -523,8 +524,8 @@ int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem) return 0; } -int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, - uint32_t ip_type, +drm_public int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, + uint32_t ip_type, uint32_t ip_instance, uint32_t ring, amdgpu_semaphore_handle sem) @@ -549,8 +550,8 @@ int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, return 0; } -int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, - uint32_t ip_type, +drm_public int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, + uint32_t ip_type, uint32_t ip_instance, uint32_t ring, amdgpu_semaphore_handle sem) @@ -595,14 +596,14 @@ static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem) return 0; } -int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) +drm_public int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) { return amdgpu_cs_unreference_sem(sem); } -int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, - uint32_t flags, - uint32_t *handle) +drm_public int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, + uint32_t flags, + uint32_t *handle) { if (NULL == dev) return -EINVAL; @@ -610,8 +611,8 @@ int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev, return drmSyncobjCreate(dev->fd, flags, handle); } -int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, - uint32_t *handle) +drm_public int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, + uint32_t *handle) { if (NULL == dev) return -EINVAL; @@ -619,8 +620,8 @@ int amdgpu_cs_create_syncobj(amdgpu_device_handle dev, return drmSyncobjCreate(dev->fd, 0, handle); } -int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, - uint32_t handle) +drm_public int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, + uint32_t handle) { if (NULL == dev) return -EINVAL; @@ -628,8 +629,9 @@ int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev, return drmSyncobjDestroy(dev->fd, handle); } -int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, - const uint32_t *syncobjs, uint32_t syncobj_count) +drm_public int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, + const uint32_t *syncobjs, + uint32_t syncobj_count) { if (NULL == dev) return -EINVAL; @@ -637,8 +639,9 @@ int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev, return drmSyncobjReset(dev->fd, syncobjs, syncobj_count); } -int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, - const uint32_t *syncobjs, uint32_t syncobj_count) +drm_public int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, + const uint32_t *syncobjs, + uint32_t syncobj_count) { if (NULL == dev) return -EINVAL; @@ -646,10 +649,10 @@ int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev, return drmSyncobjSignal(dev->fd, syncobjs, syncobj_count); } -int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, - uint32_t *handles, unsigned num_handles, - int64_t timeout_nsec, unsigned flags, - uint32_t *first_signaled) +drm_public int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, + uint32_t *handles, unsigned num_handles, + int64_t timeout_nsec, unsigned flags, + uint32_t *first_signaled) { if (NULL == dev) return -EINVAL; @@ -658,9 +661,9 @@ int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev, flags, first_signaled); } -int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, - uint32_t handle, - int *shared_fd) +drm_public int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, + uint32_t handle, + int *shared_fd) { if (NULL == dev) return -EINVAL; @@ -668,9 +671,9 @@ int amdgpu_cs_export_syncobj(amdgpu_device_handle dev, return drmSyncobjHandleToFD(dev->fd, handle, shared_fd); } -int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, - int shared_fd, - uint32_t *handle) +drm_public int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, + int shared_fd, + uint32_t *handle) { if (NULL == dev) return -EINVAL; @@ -678,9 +681,9 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev, return drmSyncobjFDToHandle(dev->fd, shared_fd, handle); } -int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, - uint32_t syncobj, - int *sync_file_fd) +drm_public int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, + uint32_t syncobj, + int *sync_file_fd) { if (NULL == dev) return -EINVAL; @@ -688,9 +691,9 @@ int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev, return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd); } -int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, - uint32_t syncobj, - int sync_file_fd) +drm_public int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, + uint32_t syncobj, + int sync_file_fd) { if (NULL == dev) return -EINVAL; @@ -698,12 +701,12 @@ int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev, return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd); } -int amdgpu_cs_submit_raw(amdgpu_device_handle dev, - amdgpu_context_handle context, - amdgpu_bo_list_handle bo_list_handle, - int num_chunks, - struct drm_amdgpu_cs_chunk *chunks, - uint64_t *seq_no) +drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev, + amdgpu_context_handle context, + amdgpu_bo_list_handle bo_list_handle, + int num_chunks, + struct drm_amdgpu_cs_chunk *chunks, + uint64_t *seq_no) { union drm_amdgpu_cs cs = {0}; uint64_t *chunk_array; @@ -728,15 +731,15 @@ int amdgpu_cs_submit_raw(amdgpu_device_handle dev, return 0; } -void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, +drm_public void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, struct drm_amdgpu_cs_chunk_data *data) { data->fence_data.handle = fence_info->handle->handle; data->fence_data.offset = fence_info->offset * sizeof(uint64_t); } -void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, - struct drm_amdgpu_cs_chunk_dep *dep) +drm_public void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, + struct drm_amdgpu_cs_chunk_dep *dep) { dep->ip_type = fence->ip_type; dep->ip_instance = fence->ip_instance; @@ -745,10 +748,10 @@ void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, dep->handle = fence->fence; } -int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, - struct amdgpu_cs_fence *fence, - uint32_t what, - uint32_t *out_handle) +drm_public int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev, + struct amdgpu_cs_fence *fence, + uint32_t what, + uint32_t *out_handle) { union drm_amdgpu_fence_to_handle fth = {0}; int r; diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 73eeeed6..362494b1 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -133,17 +133,17 @@ static void amdgpu_device_free_internal(amdgpu_device_handle dev) * // incremented. dst is freed if its reference counter is 0. */ static void amdgpu_device_reference(struct amdgpu_device **dst, - struct amdgpu_device *src) + struct amdgpu_device *src) { if (update_references(&(*dst)->refcount, &src->refcount)) amdgpu_device_free_internal(*dst); *dst = src; } -int amdgpu_device_initialize(int fd, - uint32_t *major_version, - uint32_t *minor_version, - amdgpu_device_handle *device_handle) +drm_public int amdgpu_device_initialize(int fd, + uint32_t *major_version, + uint32_t *minor_version, + amdgpu_device_handle *device_handle) { struct amdgpu_device *dev; drmVersionPtr version; @@ -279,19 +279,20 @@ cleanup: return r; } -int amdgpu_device_deinitialize(amdgpu_device_handle dev) +drm_public int amdgpu_device_deinitialize(amdgpu_device_handle dev) { amdgpu_device_reference(&dev, NULL); return 0; } -const char *amdgpu_get_marketing_name(amdgpu_device_handle dev) +drm_public const char *amdgpu_get_marketing_name(amdgpu_device_handle dev) { return dev->marketing_name; } -int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info, - void *value) +drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev, + enum amdgpu_sw_info info, + void *value) { uint32_t *val32 = (uint32_t*)value; diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c index b68e1c4f..777087f2 100644 --- a/amdgpu/amdgpu_gpu_info.c +++ b/amdgpu/amdgpu_gpu_info.c @@ -30,8 +30,8 @@ #include "amdgpu_internal.h" #include "xf86drm.h" -int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, - unsigned size, void *value) +drm_public int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, + unsigned size, void *value) { struct drm_amdgpu_info request; @@ -44,8 +44,8 @@ int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id, sizeof(struct drm_amdgpu_info)); } -int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, - int32_t *result) +drm_public int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, + int32_t *result) { struct drm_amdgpu_info request; @@ -59,9 +59,9 @@ int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id, sizeof(struct drm_amdgpu_info)); } -int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, - unsigned count, uint32_t instance, uint32_t flags, - uint32_t *values) +drm_public int amdgpu_read_mm_registers(amdgpu_device_handle dev, + unsigned dword_offset, unsigned count, uint32_t instance, + uint32_t flags, uint32_t *values) { struct drm_amdgpu_info request; @@ -78,8 +78,9 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, sizeof(struct drm_amdgpu_info)); } -int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, - uint32_t *count) +drm_public int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, + unsigned type, + uint32_t *count) { struct drm_amdgpu_info request; @@ -93,9 +94,9 @@ int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type, sizeof(struct drm_amdgpu_info)); } -int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, - unsigned ip_instance, - struct drm_amdgpu_info_hw_ip *info) +drm_public int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, + unsigned ip_instance, + struct drm_amdgpu_info_hw_ip *info) { struct drm_amdgpu_info request; @@ -110,9 +111,9 @@ int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, sizeof(struct drm_amdgpu_info)); } -int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type, - unsigned ip_instance, unsigned index, - uint32_t *version, uint32_t *feature) +drm_public int amdgpu_query_firmware_version(amdgpu_device_handle dev, + unsigned fw_type, unsigned ip_instance, unsigned index, + uint32_t *version, uint32_t *feature) { struct drm_amdgpu_info request; struct drm_amdgpu_info_firmware firmware = {}; @@ -227,8 +228,8 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) return 0; } -int amdgpu_query_gpu_info(amdgpu_device_handle dev, - struct amdgpu_gpu_info *info) +drm_public int amdgpu_query_gpu_info(amdgpu_device_handle dev, + struct amdgpu_gpu_info *info) { if (!dev || !info) return -EINVAL; @@ -239,10 +240,10 @@ int amdgpu_query_gpu_info(amdgpu_device_handle dev, return 0; } -int amdgpu_query_heap_info(amdgpu_device_handle dev, - uint32_t heap, - uint32_t flags, - struct amdgpu_heap_info *info) +drm_public int amdgpu_query_heap_info(amdgpu_device_handle dev, + uint32_t heap, + uint32_t flags, + struct amdgpu_heap_info *info) { struct drm_amdgpu_info_vram_gtt vram_gtt_info = {}; int r; @@ -291,8 +292,8 @@ int amdgpu_query_heap_info(amdgpu_device_handle dev, return 0; } -int amdgpu_query_gds_info(amdgpu_device_handle dev, - struct amdgpu_gds_resource_info *gds_info) +drm_public int amdgpu_query_gds_info(amdgpu_device_handle dev, + struct amdgpu_gds_resource_info *gds_info) { struct drm_amdgpu_info_gds gds_config = {}; int r; @@ -316,8 +317,8 @@ int amdgpu_query_gds_info(amdgpu_device_handle dev, return 0; } -int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, - unsigned size, void *value) +drm_public int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type, + unsigned size, void *value) { struct drm_amdgpu_info request; diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 1de9f952..d25d4216 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -29,9 +29,9 @@ #include "amdgpu_internal.h" #include "util_math.h" -int amdgpu_va_range_query(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range type, - uint64_t *start, uint64_t *end) +drm_public int amdgpu_va_range_query(amdgpu_device_handle dev, + enum amdgpu_gpu_va_range type, + uint64_t *start, uint64_t *end) { if (type != amdgpu_gpu_va_range_general) return -EINVAL; @@ -186,14 +186,14 @@ out: pthread_mutex_unlock(&mgr->bo_va_mutex); } -int amdgpu_va_range_alloc(amdgpu_device_handle dev, - enum amdgpu_gpu_va_range va_range_type, - uint64_t size, - uint64_t va_base_alignment, - uint64_t va_base_required, - uint64_t *va_base_allocated, - amdgpu_va_handle *va_range_handle, - uint64_t flags) +drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev, + enum amdgpu_gpu_va_range va_range_type, + uint64_t size, + uint64_t va_base_alignment, + uint64_t va_base_required, + uint64_t *va_base_allocated, + amdgpu_va_handle *va_range_handle, + uint64_t flags) { struct amdgpu_bo_va_mgr *vamgr; @@ -250,7 +250,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, return 0; } -int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) +drm_public int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) { if(!va_range_handle || !va_range_handle->address) return 0; diff --git a/amdgpu/amdgpu_vm.c b/amdgpu/amdgpu_vm.c index da9d07f8..7e6e28f0 100644 --- a/amdgpu/amdgpu_vm.c +++ b/amdgpu/amdgpu_vm.c @@ -26,7 +26,7 @@ #include "xf86drm.h" #include "amdgpu_internal.h" -int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags) +drm_public int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags) { union drm_amdgpu_vm vm; @@ -37,7 +37,8 @@ int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags) &vm, sizeof(vm)); } -int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags) +drm_public int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, + uint32_t flags) { union drm_amdgpu_vm vm;