geemili
/
drm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

RADEON: cleanup radeon_do_engine_reset()

main
Alex Deucher 2008-05-12 09:35:06 -04:00
parent 5532b8d2a0
commit e16a7101e8
1 changed files with 28 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
shared-core/radeon_cp.c
View File

@ -16480,12 +16480,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
static int radeon_do_engine_reset(struct drm_device * dev) static int radeon_do_engine_reset(struct drm_device * dev)
{ {
drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_private_t *dev_priv = dev->dev_private;
u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
DRM_DEBUG("\n"); DRM_DEBUG("\n");
radeon_do_pixcache_flush(dev_priv); radeon_do_pixcache_flush(dev_priv);
if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
/* may need something similar for newer chips */
clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
@ -16496,28 +16497,30 @@ static int radeon_do_engine_reset(struct drm_device * dev)
RADEON_FORCEON_YCLKB | RADEON_FORCEON_YCLKB |
RADEON_FORCEON_MC | RADEON_FORCEON_MC |
RADEON_FORCEON_AIC)); RADEON_FORCEON_AIC));
}
rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_CP |
RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_HI |
RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_SE |
RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_RE |
RADEON_SOFT_RESET_PP | RADEON_SOFT_RESET_PP |
RADEON_SOFT_RESET_E2 | RADEON_SOFT_RESET_E2 |
RADEON_SOFT_RESET_RB)); RADEON_SOFT_RESET_RB));
RADEON_READ(RADEON_RBBM_SOFT_RESET); RADEON_READ(RADEON_RBBM_SOFT_RESET);
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
~(RADEON_SOFT_RESET_CP | ~(RADEON_SOFT_RESET_CP |
RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_HI |
RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_SE |
RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_RE |
RADEON_SOFT_RESET_PP | RADEON_SOFT_RESET_PP |
RADEON_SOFT_RESET_E2 | RADEON_SOFT_RESET_E2 |
RADEON_SOFT_RESET_RB))); RADEON_SOFT_RESET_RB)));
RADEON_READ(RADEON_RBBM_SOFT_RESET); RADEON_READ(RADEON_RBBM_SOFT_RESET);
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);