RADEON: cleanup radeon_do_engine_reset()
parent
5532b8d2a0
commit
e16a7101e8
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@ -16480,12 +16480,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
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static int radeon_do_engine_reset(struct drm_device * dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
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u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
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DRM_DEBUG("\n");
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radeon_do_pixcache_flush(dev_priv);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
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if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
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/* may need something similar for newer chips */
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clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
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mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
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@ -16496,6 +16497,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
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RADEON_FORCEON_YCLKB |
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RADEON_FORCEON_MC |
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RADEON_FORCEON_AIC));
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}
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rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
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@ -16518,6 +16520,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
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RADEON_SOFT_RESET_RB)));
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RADEON_READ(RADEON_RBBM_SOFT_RESET);
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if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
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RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
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RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
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RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
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