nouveau: small RAMFC cleanups
parent
1c32fecd6d
commit
e26ec51146
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@ -28,10 +28,10 @@
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#include "drm.h"
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#include "nouveau_drv.h"
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#define NV04_RAMFC dev_priv->ramfc_offset
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#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV04_RAMFC_##offset, (val))
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#define RAMFC_RD(offset) NV_RI32(fifoctx + NV04_RAMFC_##offset)
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#define NV04_FIFO_CONTEXT_SIZE 32
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#define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))
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#define NV04_RAMFC__SIZE 32
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int
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nv04_fifo_create_context(drm_device_t *dev, int channel)
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@ -39,14 +39,14 @@ nv04_fifo_create_context(drm_device_t *dev, int channel)
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[channel];
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struct nouveau_object *pb = chan->cmdbuf_obj;
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int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE);
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uint32_t fifoctx = NV04_RAMFC(channel);
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int i;
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if (!pb || !pb->instance)
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return DRM_ERR(EINVAL);
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/* Clear RAMFC */
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for (i=0; i<NV04_FIFO_CONTEXT_SIZE; i+=4)
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for (i=0; i<NV04_RAMFC__SIZE; i+=4)
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NV_WI32(fifoctx + i, 0);
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/* Setup initial state */
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@ -67,11 +67,10 @@ void
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nv04_fifo_destroy_context(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint32_t fifoctx;
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uint32_t fifoctx = NV04_RAMFC(channel);
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int i;
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fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE);
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for (i=0; i<NV04_FIFO_CONTEXT_SIZE; i+=4)
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for (i=0; i<NV04_RAMFC__SIZE; i+=4)
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NV_WI32(fifoctx + i, 0);
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}
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@ -79,7 +78,7 @@ int
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nv04_fifo_load_context(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE);
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uint32_t fifoctx = NV04_RAMFC(channel);
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uint32_t tmp;
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NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | channel);
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@ -107,7 +106,7 @@ int
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nv04_fifo_save_context(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE);
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uint32_t fifoctx = NV04_RAMFC(channel);
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uint32_t tmp;
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RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT);
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@ -30,17 +30,18 @@
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#define RAMFC_WR(offset, val) NV_WI32(fifoctx + NV40_RAMFC_##offset, (val))
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#define RAMFC_RD(offset) NV_RI32(fifoctx + NV40_RAMFC_##offset)
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#define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c)*NV40_RAMFC__SIZE))
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#define NV40_RAMFC__SIZE 128
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int
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nv40_fifo_create_context(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[channel];
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uint32_t fifoctx, grctx, pushbuf;
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uint32_t fifoctx = NV40_RAMFC(channel), grctx, pushbuf;
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int i;
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fifoctx = dev_priv->ramfc_offset + channel*128;
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for (i=0;i<128;i+=4)
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for (i = 0; i < NV40_RAMFC__SIZE; i+=4)
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NV_WI32(fifoctx + i, 0);
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grctx = nouveau_chip_instance_get(dev, chan->ramin_grctx);
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@ -70,11 +71,10 @@ void
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nv40_fifo_destroy_context(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint32_t fifoctx;
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uint32_t fifoctx = NV40_RAMFC(channel);
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int i;
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fifoctx = dev_priv->ramfc_offset + channel*128;
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for (i=0;i<128;i+=4)
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for (i = 0; i < NV40_RAMFC__SIZE; i+=4)
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NV_WI32(fifoctx + i, 0);
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}
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@ -82,11 +82,9 @@ int
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nv40_fifo_load_context(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint32_t fifoctx;
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uint32_t fifoctx = NV40_RAMFC(channel);
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uint32_t tmp, tmp2;
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fifoctx = dev_priv->ramfc_offset + channel*128;
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NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET));
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NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT));
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NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT , RAMFC_RD(REF_CNT));
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@ -143,11 +141,9 @@ int
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nv40_fifo_save_context(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint32_t fifoctx;
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uint32_t fifoctx = NV40_RAMFC(channel);
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uint32_t tmp;
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fifoctx = dev_priv->ramfc_offset + channel*128;
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RAMFC_WR(DMA_PUT , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
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RAMFC_WR(DMA_GET , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
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RAMFC_WR(REF_CNT , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
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