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intel: Convert to untiled pitches if surface is too large for tiling. 

If the pitch is too large for the hardware to tile, recompute the
required surface size based on the untiled pitch and alignments. For the
older hardware, which has smaller limits and greater restrictions, this
may be a considerable saving in allocation size.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
main
Chris Wilson 2010-06-09 10:08:41 +01:00
parent f179137f8f
commit e65caeba9e
1 changed files with 30 additions and 22 deletions
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18
intel/intel_bufmgr_gem.c
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@ -689,9 +689,15 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
drm_intel_bo *bo;
unsigned long size, stride, aligned_y = y;
unsigned long size, stride;
uint32_t tiling;
int ret;
do {
unsigned long aligned_y;
tiling = *tiling_mode;
/* If we're tiled, our allocations are in 8 or 32-row blocks,
* so failure to align our height means that we won't allocate
* enough pages.
@ -703,17 +709,19 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
* documented on 965, and may be the case on older chipsets
* too so we try to be careful.
*/
if (*tiling_mode == I915_TILING_NONE)
aligned_y = y;
if (tiling == I915_TILING_NONE)
aligned_y = ALIGN(y, 2);
else if (*tiling_mode == I915_TILING_X)
else if (tiling == I915_TILING_X)
aligned_y = ALIGN(y, 8);
else if (*tiling_mode == I915_TILING_Y)
else if (tiling == I915_TILING_Y)
aligned_y = ALIGN(y, 32);
stride = x * cpp;
stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling);
size = stride * aligned_y;
size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
} while (*tiling_mode != tiling);
bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
if (!bo)