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[i915] clean up whinging from checkpatch.pl

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Keith Packard 2008-05-08 11:45:53 -07:00
parent 07ad5ce1e1
commit ec75369b40
1 changed files with 218 additions and 192 deletions
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242
linux-core/i915_gem.c
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@ -64,11 +64,10 @@ i915_gem_object_free_page_list(struct drm_gem_object *obj)
return; return;
for (i = 0; i < page_count; i++) { for (i = 0; i < page_count; i++)
if (obj_priv->page_list[i] != NULL) { if (obj_priv->page_list[i] != NULL)
page_cache_release(obj_priv->page_list[i]); page_cache_release(obj_priv->page_list[i]);
}
}
drm_free(obj_priv->page_list, drm_free(obj_priv->page_list,
page_count * sizeof(struct page *), page_count * sizeof(struct page *),
DRM_MEM_DRIVER); DRM_MEM_DRIVER);
@ -76,49 +75,59 @@ i915_gem_object_free_page_list(struct drm_gem_object *obj)
} }
static void static void
i915_gem_flush(struct drm_device *dev, uint32_t invalidate_domains, uint32_t flush_domains) i915_gem_flush(struct drm_device *dev,
uint32_t invalidate_domains,
uint32_t flush_domains)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
uint32_t cmd; uint32_t cmd;
RING_LOCALS; RING_LOCALS;
#if WATCH_EXEC #if WATCH_EXEC
DRM_INFO ("%s: invalidate %08x flush %08x\n", __FUNCTION__, DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
invalidate_domains, flush_domains); invalidate_domains, flush_domains);
#endif #endif
if (flush_domains & DRM_GEM_DOMAIN_CPU) if (flush_domains & DRM_GEM_DOMAIN_CPU)
drm_agp_chipset_flush(dev); drm_agp_chipset_flush(dev);
if ((invalidate_domains|flush_domains) & ~DRM_GEM_DOMAIN_CPU) if ((invalidate_domains|flush_domains) & ~DRM_GEM_DOMAIN_CPU) {
{ /*
/* read/write caches: * read/write caches:
*
* DRM_GEM_DOMAIN_I915_RENDER is always invalidated, but is * DRM_GEM_DOMAIN_I915_RENDER is always invalidated, but is
* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is also * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
* flushed at 2d versus 3d pipeline switches. * also flushed at 2d versus 3d pipeline switches.
* *
* read-only caches: * read-only caches:
* DRM_GEM_DOMAIN_I915_SAMPLER is flushed on pre-965 if MI_READ_FLUSH *
* is set, and is always flushed on 965. * DRM_GEM_DOMAIN_I915_SAMPLER is flushed on pre-965 if
* MI_READ_FLUSH is set, and is always flushed on 965.
*
* DRM_GEM_DOMAIN_I915_COMMAND may not exist? * DRM_GEM_DOMAIN_I915_COMMAND may not exist?
* DRM_GEM_DOMAIN_I915_INSTRUCTION, which exists on 965, is invalidated *
* when MI_EXE_FLUSH is set. * DRM_GEM_DOMAIN_I915_INSTRUCTION, which exists on 965, is
* DRM_GEM_DOMAIN_I915_VERTEX, which exists on 965, is invalidated with * invalidated when MI_EXE_FLUSH is set.
* every MI_FLUSH. *
* DRM_GEM_DOMAIN_I915_VERTEX, which exists on 965, is
* invalidated with every MI_FLUSH.
* *
* TLBs: * TLBs:
* On 965, TLBs associated with DRM_GEM_DOMAIN_I915_COMMAND and *
* DRM_GEM_DOMAIN_CPU in are invalidated at PTE write and * On 965, TLBs associated with DRM_GEM_DOMAIN_I915_COMMAND
* DRM_GEM_DOMAIN_I915_RENDER and DRM_GEM_DOMAIN_I915_SAMPLER are * and DRM_GEM_DOMAIN_CPU in are invalidated at PTE write and
* flushed at any MI_FLUSH. * DRM_GEM_DOMAIN_I915_RENDER and DRM_GEM_DOMAIN_I915_SAMPLER
* are flushed at any MI_FLUSH.
*/ */
cmd = CMD_MI_FLUSH | MI_NO_WRITE_FLUSH; cmd = CMD_MI_FLUSH | MI_NO_WRITE_FLUSH;
if ((invalidate_domains|flush_domains) & DRM_GEM_DOMAIN_I915_RENDER) if ((invalidate_domains|flush_domains) &
DRM_GEM_DOMAIN_I915_RENDER)
cmd &= ~MI_NO_WRITE_FLUSH; cmd &= ~MI_NO_WRITE_FLUSH;
if (!IS_I965G(dev)) { if (!IS_I965G(dev)) {
/* On the 965, the sampler cache always gets flushed and this /*
* bit is reserved. * On the 965, the sampler cache always gets flushed
* and this bit is reserved.
*/ */
if (invalidate_domains & DRM_GEM_DOMAIN_I915_SAMPLER) if (invalidate_domains & DRM_GEM_DOMAIN_I915_SAMPLER)
cmd |= MI_READ_FLUSH; cmd |= MI_READ_FLUSH;
@ -147,11 +156,10 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
/* If there are writes queued to the buffer, flush and /* If there are writes queued to the buffer, flush and
* create a new cookie to wait for. * create a new cookie to wait for.
*/ */
if (obj->write_domain & ~(DRM_GEM_DOMAIN_CPU)) if (obj->write_domain & ~(DRM_GEM_DOMAIN_CPU)) {
{
#if WATCH_BUF #if WATCH_BUF
DRM_INFO("%s: flushing object %p from write domain %08x\n", DRM_INFO("%s: flushing object %p from write domain %08x\n",
__FUNCTION__, obj, obj->write_domain); __func__, obj, obj->write_domain);
#endif #endif
i915_gem_flush(dev, 0, obj->write_domain); i915_gem_flush(dev, 0, obj->write_domain);
obj->write_domain = 0; obj->write_domain = 0;
@ -165,7 +173,7 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
if (obj_priv->last_rendering_cookie != 0) { if (obj_priv->last_rendering_cookie != 0) {
#if WATCH_BUF #if WATCH_BUF
DRM_INFO("%s: object %p wait for cookie %08x\n", DRM_INFO("%s: object %p wait for cookie %08x\n",
__FUNCTION__, obj, obj_priv->last_rendering_cookie); __func__, obj, obj_priv->last_rendering_cookie);
#endif #endif
ret = i915_wait_irq(dev, obj_priv->last_rendering_cookie); ret = i915_wait_irq(dev, obj_priv->last_rendering_cookie);
if (ret != 0) if (ret != 0)
@ -173,7 +181,10 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj)
/* Clear it now that we know it's passed. */ /* Clear it now that we know it's passed. */
obj_priv->last_rendering_cookie = 0; obj_priv->last_rendering_cookie = 0;
/* The cookie held a reference to the object, release that now */ /*
* The cookie held a reference to the object,
* release that now
*/
drm_gem_object_unreference(obj); drm_gem_object_unreference(obj);
} }
@ -189,7 +200,7 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
struct drm_i915_gem_object *obj_priv = obj->driver_private; struct drm_i915_gem_object *obj_priv = obj->driver_private;
#if WATCH_BUF #if WATCH_BUF
DRM_INFO ("%s:%d %p\n", __FUNCTION__, __LINE__, obj); DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
#endif #endif
if (obj_priv->gtt_space == NULL) if (obj_priv->gtt_space == NULL)
@ -212,7 +223,8 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
#if WATCH_BUF | WATCH_EXEC #if WATCH_BUF | WATCH_EXEC
static void static void
i915_gem_dump_page (struct page *page, uint32_t start, uint32_t end, uint32_t bias, uint32_t mark) i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
uint32_t bias, uint32_t mark)
{ {
uint32_t *mem = kmap_atomic(page, KM_USER0); uint32_t *mem = kmap_atomic(page, KM_USER0);
int i; int i;
@ -226,14 +238,14 @@ i915_gem_dump_page (struct page *page, uint32_t start, uint32_t end, uint32_t bi
} }
static void static void
i915_gem_dump_object (struct drm_gem_object *obj, int len, const char *where, uint32_t mark) i915_gem_dump_object(struct drm_gem_object *obj, int len,
const char *where, uint32_t mark)
{ {
struct drm_i915_gem_object *obj_priv = obj->driver_private; struct drm_i915_gem_object *obj_priv = obj->driver_private;
int page; int page;
DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset); DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset);
for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) {
{
int page_len, chunk, chunk_len; int page_len, chunk, chunk_len;
page_len = len - page * PAGE_SIZE; page_len = len - page * PAGE_SIZE;
@ -246,7 +258,8 @@ i915_gem_dump_object (struct drm_gem_object *obj, int len, const char *where, ui
chunk_len = 128; chunk_len = 128;
i915_gem_dump_page(obj_priv->page_list[page], i915_gem_dump_page(obj_priv->page_list[page],
chunk, chunk + chunk_len, chunk, chunk + chunk_len,
obj_priv->gtt_offset + page * PAGE_SIZE, obj_priv->gtt_offset +
page * PAGE_SIZE,
mark); mark);
} }
} }
@ -262,7 +275,8 @@ i915_dump_lru (struct drm_device *dev, const char *where)
DRM_INFO("GTT LRU %s {\n", where); DRM_INFO("GTT LRU %s {\n", where);
list_for_each_entry(obj_priv, &dev_priv->mm.gtt_lru, gtt_lru_entry) { list_for_each_entry(obj_priv, &dev_priv->mm.gtt_lru, gtt_lru_entry) {
DRM_INFO (" %p: %08x\n", obj_priv, obj_priv->last_rendering_cookie); DRM_INFO(" %p: %08x\n", obj_priv,
obj_priv->last_rendering_cookie);
} }
DRM_INFO("}\n"); DRM_INFO("}\n");
} }
@ -283,7 +297,7 @@ i915_gem_evict_something(struct drm_device *dev)
gtt_lru_entry); gtt_lru_entry);
obj = obj_priv->obj; obj = obj_priv->obj;
#if WATCH_LRU #if WATCH_LRU
DRM_INFO ("%s: evicting %p\n", __FUNCTION__, obj); DRM_INFO("%s: evicting %p\n", __func__, obj);
#endif #endif
/* Only unpinned buffers should be on this list. */ /* Only unpinned buffers should be on this list. */
@ -300,7 +314,7 @@ i915_gem_evict_something(struct drm_device *dev)
/* Wait on the rendering and unbind the buffer. */ /* Wait on the rendering and unbind the buffer. */
i915_gem_object_unbind(obj); i915_gem_object_unbind(obj);
#if WATCH_LRU #if WATCH_LRU
DRM_INFO ("%s: evicted %p\n", __FUNCTION__, obj); DRM_INFO("%s: evicted %p\n", __func__, obj);
#endif #endif
return 0; return 0;
@ -343,7 +357,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
* fitting our object in, we're out of memory. * fitting our object in, we're out of memory.
*/ */
#if WATCH_LRU #if WATCH_LRU
DRM_INFO ("%s: GTT full, evicting something\n", __FUNCTION__); DRM_INFO("%s: GTT full, evicting something\n", __func__);
#endif #endif
if (list_empty(&dev_priv->mm.gtt_lru)) { if (list_empty(&dev_priv->mm.gtt_lru)) {
DRM_ERROR("GTT full, but LRU list empty\n"); DRM_ERROR("GTT full, but LRU list empty\n");
@ -357,7 +371,8 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
} }
#if WATCH_BUF #if WATCH_BUF
DRM_INFO ("Binding object of size %d at 0x%08x\n", obj->size, obj_priv->gtt_offset); DRM_INFO("Binding object of size %d at 0x%08x\n",
obj->size, obj_priv->gtt_offset);
#endif #endif
/* Get the list of pages out of our struct file. They'll be pinned /* Get the list of pages out of our struct file. They'll be pinned
@ -441,7 +456,7 @@ i915_gem_object_set_domain (struct drm_gem_object *obj,
#if WATCH_BUF #if WATCH_BUF
DRM_INFO("%s: object %p read %08x write %08x\n", DRM_INFO("%s: object %p read %08x write %08x\n",
__FUNCTION__, obj, read_domains, write_domain); __func__, obj, read_domains, write_domain);
#endif #endif
/* /*
* Flush the current write domain if * Flush the current write domain if
@ -449,8 +464,7 @@ i915_gem_object_set_domain (struct drm_gem_object *obj,
* any read domains which differ from the old * any read domains which differ from the old
* write domain * write domain
*/ */
if (obj->write_domain && obj->write_domain != read_domains) if (obj->write_domain && obj->write_domain != read_domains) {
{
flush_domains |= obj->write_domain; flush_domains |= obj->write_domain;
invalidate_domains |= read_domains & ~obj->write_domain; invalidate_domains |= read_domains & ~obj->write_domain;
} }
@ -459,11 +473,10 @@ i915_gem_object_set_domain (struct drm_gem_object *obj,
* stale data. That is, any new read domains. * stale data. That is, any new read domains.
*/ */
invalidate_domains |= read_domains & ~obj->read_domains; invalidate_domains |= read_domains & ~obj->read_domains;
if ((flush_domains | invalidate_domains) & DRM_GEM_DOMAIN_CPU) if ((flush_domains | invalidate_domains) & DRM_GEM_DOMAIN_CPU) {
{
#if WATCH_BUF #if WATCH_BUF
DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
__FUNCTION__, flush_domains, invalidate_domains); __func__, flush_domains, invalidate_domains);
#endif #endif
/* /*
* If we're invaliding the CPU cache and flushing a GPU cache, * If we're invaliding the CPU cache and flushing a GPU cache,
@ -494,13 +507,16 @@ i915_gem_dev_set_domain (struct drm_device *dev)
* Now that all the buffers are synced to the proper domains, * Now that all the buffers are synced to the proper domains,
* flush and invalidate the collected domains * flush and invalidate the collected domains
*/ */
if (dev->invalidate_domains | dev->flush_domains) if (dev->invalidate_domains | dev->flush_domains) {
{
#if WATCH_EXEC #if WATCH_EXEC
DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
__FUNCTION__, dev->invalidate_domains, dev->flush_domains); __func__,
dev->invalidate_domains,
dev->flush_domains);
#endif #endif
i915_gem_flush (dev, dev->invalidate_domains, dev->flush_domains); i915_gem_flush(dev,
dev->invalidate_domains,
dev->flush_domains);
dev->invalidate_domains = 0; dev->invalidate_domains = 0;
dev->flush_domains = 0; dev->flush_domains = 0;
} }
@ -532,15 +548,18 @@ i915_gem_reloc_and_validate_object(struct drm_gem_object *obj,
if (obj_priv->pin_count == 0) { if (obj_priv->pin_count == 0) {
/* Move our buffer to the head of the LRU. */ /* Move our buffer to the head of the LRU. */
if (list_empty(&obj_priv->gtt_lru_entry)) if (list_empty(&obj_priv->gtt_lru_entry))
list_add_tail(&obj_priv->gtt_lru_entry, &dev_priv->mm.gtt_lru); list_add_tail(&obj_priv->gtt_lru_entry,
&dev_priv->mm.gtt_lru);
else else
list_move_tail(&obj_priv->gtt_lru_entry, &dev_priv->mm.gtt_lru); list_move_tail(&obj_priv->gtt_lru_entry,
&dev_priv->mm.gtt_lru);
#if WATCH_LRU && 0 #if WATCH_LRU && 0
i915_dump_lru (dev, __FUNCTION__); i915_dump_lru(dev, __func__);
#endif #endif
} }
relocs = (struct drm_i915_gem_relocation_entry __user *) (uintptr_t) entry->relocs_ptr; relocs = (struct drm_i915_gem_relocation_entry __user *)
(uintptr_t) entry->relocs_ptr;
/* Apply the relocations, using the GTT aperture to avoid cache /* Apply the relocations, using the GTT aperture to avoid cache
* flushing requirements. * flushing requirements.
*/ */
@ -571,31 +590,40 @@ i915_gem_reloc_and_validate_object(struct drm_gem_object *obj,
} }
if (reloc.offset > obj->size - 4) { if (reloc.offset > obj->size - 4) {
DRM_ERROR("Relocation beyond object bounds: obj %p target %d offset %d size %d.\n", DRM_ERROR("Relocation beyond object bounds: "
obj, reloc.target_handle, (int) reloc.offset, (int) obj->size); "obj %p target %d offset %d size %d.\n",
obj, reloc.target_handle,
(int) reloc.offset, (int) obj->size);
drm_gem_object_unreference(target_obj); drm_gem_object_unreference(target_obj);
return -EINVAL; return -EINVAL;
} }
if (reloc.offset & 3) { if (reloc.offset & 3) {
DRM_ERROR("Relocation not 4-byte aligned: obj %p target %d offset %d.\n", DRM_ERROR("Relocation not 4-byte aligned: "
obj, reloc.target_handle, (int) reloc.offset); "obj %p target %d offset %d.\n",
obj, reloc.target_handle,
(int) reloc.offset);
drm_gem_object_unreference(target_obj); drm_gem_object_unreference(target_obj);
return -EINVAL; return -EINVAL;
} }
if (reloc.write_domain && target_obj->pending_write_domain && if (reloc.write_domain && target_obj->pending_write_domain &&
reloc.write_domain != target_obj->pending_write_domain) reloc.write_domain != target_obj->pending_write_domain) {
{ DRM_ERROR("Write domain conflict: "
DRM_ERROR("Write domain conflict: obj %p target %d offset %d new %08x old %08x\n", "obj %p target %d offset %d "
obj, reloc.target_handle, (int) reloc.offset, "new %08x old %08x\n",
reloc.write_domain, target_obj->pending_write_domain); obj, reloc.target_handle,
(int) reloc.offset,
reloc.write_domain,
target_obj->pending_write_domain);
drm_gem_object_unreference(target_obj); drm_gem_object_unreference(target_obj);
return -EINVAL; return -EINVAL;
} }
#if WATCH_RELOC #if WATCH_RELOC
DRM_INFO ("%s: obj %p offset %08x target %d read %08x write %08x gtt %08x presumed %08x delta %08x\n", DRM_INFO("%s: obj %p offset %08x target %d "
__FUNCTION__, "read %08x write %08x gtt %08x "
"presumed %08x delta %08x\n",
__func__,
obj, obj,
(int) reloc.offset, (int) reloc.offset,
(int) reloc.target_handle, (int) reloc.target_handle,
@ -624,8 +652,7 @@ i915_gem_reloc_and_validate_object(struct drm_gem_object *obj,
/* As we're writing through the gtt, flush /* As we're writing through the gtt, flush
* any CPU writes before we write the relocations * any CPU writes before we write the relocations
*/ */
if (obj->write_domain & DRM_GEM_DOMAIN_CPU) if (obj->write_domain & DRM_GEM_DOMAIN_CPU) {
{
i915_gem_clflush_object(obj); i915_gem_clflush_object(obj);
drm_agp_chipset_flush(dev); drm_agp_chipset_flush(dev);
obj->write_domain = 0; obj->write_domain = 0;
@ -669,7 +696,7 @@ i915_gem_reloc_and_validate_object(struct drm_gem_object *obj,
iounmap(reloc_page); iounmap(reloc_page);
#if WATCH_BUF #if WATCH_BUF
i915_gem_dump_object (obj, 128, __FUNCTION__, ~0); i915_gem_dump_object(obj, 128, __func__, ~0);
#endif #endif
return 0; return 0;
} }
@ -680,7 +707,8 @@ i915_dispatch_gem_execbuffer (struct drm_device * dev,
uint64_t exec_offset) uint64_t exec_offset)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *) (uintptr_t) exec->cliprects_ptr; struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
(uintptr_t) exec->cliprects_ptr;
int nbox = exec->num_cliprects; int nbox = exec->num_cliprects;
int i = 0, count; int i = 0, count;
uint32_t exec_start, exec_len; uint32_t exec_start, exec_len;
@ -710,10 +738,13 @@ i915_dispatch_gem_execbuffer (struct drm_device * dev,
if (dev_priv->use_mi_batchbuffer_start) { if (dev_priv->use_mi_batchbuffer_start) {
BEGIN_LP_RING(2); BEGIN_LP_RING(2);
if (IS_I965G(dev)) { if (IS_I965G(dev)) {
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); OUT_RING(MI_BATCH_BUFFER_START |
(2 << 6) |
MI_BATCH_NON_SECURE_I965);
OUT_RING(exec_start); OUT_RING(exec_start);
} else { } else {
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); OUT_RING(MI_BATCH_BUFFER_START |
(2 << 6));
OUT_RING(exec_start | MI_BATCH_NON_SECURE); OUT_RING(exec_start | MI_BATCH_NON_SECURE);
} }
ADVANCE_LP_RING(); ADVANCE_LP_RING();
@ -739,25 +770,13 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
struct drm_i915_gem_execbuffer *args = data; struct drm_i915_gem_execbuffer *args = data;
struct drm_i915_gem_validate_entry *validate_list; struct drm_i915_gem_validate_entry *validate_list;
struct drm_gem_object **object_list; struct drm_gem_object **object_list;
struct drm_gem_object *batch_obj;
int ret, i; int ret, i;
uint64_t exec_offset; uint64_t exec_offset;
uint32_t cookie; uint32_t cookie;
LOCK_TEST_WITH_RETURN(dev, file_priv); LOCK_TEST_WITH_RETURN(dev, file_priv);
#if 0
/*
* XXX wait for previous rendering to complete as we otherwise never
* flush the LRU list
*/
{
drm_i915_private_t *dev_priv = dev->dev_private;
while (!list_empty (&dev_priv->mm.gtt_lru))
i915_gem_evict_something (dev);
}
#endif
#if WATCH_EXEC #if WATCH_EXEC
DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
(int) args->buffers_ptr, args->buffer_count, args->batch_len); (int) args->buffers_ptr, args->buffer_count, args->batch_len);
@ -770,24 +789,27 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
object_list = drm_calloc(sizeof(*object_list), args->buffer_count, object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
DRM_MEM_DRIVER); DRM_MEM_DRIVER);
if (validate_list == NULL || object_list == NULL) { if (validate_list == NULL || object_list == NULL) {
DRM_ERROR ("Failed to allocate validate or object list for %d buffers\n", DRM_ERROR("Failed to allocate validate or object list "
"for %d buffers\n",
args->buffer_count); args->buffer_count);
ret = -ENOMEM; ret = -ENOMEM;
goto err; goto err;
} }
ret = copy_from_user(validate_list, ret = copy_from_user(validate_list,
(struct drm_i915_relocation_entry __user*)(uintptr_t) (struct drm_i915_relocation_entry __user *)
args->buffers_ptr, (uintptr_t) args->buffers_ptr,
sizeof(*validate_list) * args->buffer_count); sizeof(*validate_list) * args->buffer_count);
if (ret != 0) { if (ret != 0) {
DRM_ERROR ("copy %d validate entries failed %d\n", args->buffer_count, ret); DRM_ERROR("copy %d validate entries failed %d\n",
args->buffer_count, ret);
goto err; goto err;
} }
/* Look up object handles and perform the relocations */ /* Look up object handles and perform the relocations */
for (i = 0; i < args->buffer_count; i++) { for (i = 0; i < args->buffer_count; i++) {
object_list[i] = drm_gem_object_lookup(dev, file_priv, object_list[i] = drm_gem_object_lookup(dev, file_priv,
validate_list[i].buffer_handle); validate_list[i].
buffer_handle);
if (object_list[i] == NULL) { if (object_list[i] == NULL) {
DRM_ERROR("Invalid object handle %d at index %d\n", DRM_ERROR("Invalid object handle %d at index %d\n",
validate_list[i].buffer_handle, i); validate_list[i].buffer_handle, i);
@ -795,7 +817,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
goto err; goto err;
} }
ret = i915_gem_reloc_and_validate_object(object_list[i], file_priv, ret = i915_gem_reloc_and_validate_object(object_list[i],
file_priv,
&validate_list[i]); &validate_list[i]);
if (ret) { if (ret) {
DRM_ERROR("reloc and validate failed %d\n", ret); DRM_ERROR("reloc and validate failed %d\n", ret);
@ -804,8 +827,9 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
} }
/* Set the pending read domains for the batch buffer to COMMAND */ /* Set the pending read domains for the batch buffer to COMMAND */
object_list[args->buffer_count-1]->pending_read_domains = DRM_GEM_DOMAIN_I915_COMMAND; batch_obj = object_list[args->buffer_count-1];
object_list[args->buffer_count-1]->pending_write_domain = 0; batch_obj->pending_read_domains = DRM_GEM_DOMAIN_I915_COMMAND;
batch_obj->pending_write_domain = 0;
for (i = 0; i < args->buffer_count; i++) { for (i = 0; i < args->buffer_count; i++) {
struct drm_gem_object *obj = object_list[i]; struct drm_gem_object *obj = object_list[i];
@ -837,23 +861,23 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
#if WATCH_EXEC #if WATCH_EXEC
i915_gem_dump_object(object_list[args->buffer_count - 1], i915_gem_dump_object(object_list[args->buffer_count - 1],
args->batch_len, args->batch_len,
__FUNCTION__, __func__,
~0); ~0);
#endif #endif
/* Exec the batchbuffer */ /* Exec the batchbuffer */
ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset); ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
if (ret) if (ret) {
{
DRM_ERROR("dispatch failed %d\n", ret); DRM_ERROR("dispatch failed %d\n", ret);
goto err; goto err;
} }
/* Get a cookie representing the execution of the current buffer, which we /*
* can wait on. We would like to mitigate these interrupts, likely by * Get a cookie representing the execution of the current buffer,
* only creating cookies occasionally (so that we have *some* interrupts * which we can wait on. We would like to mitigate these interrupts,
* representing completion of buffers that we can wait on when trying * likely by only creating cookies occasionally (so that we have
* to clear up gtt space). * *some* interrupts representing completion of buffers that we can
* wait on when trying to clear up gtt space).
*/ */
cookie = i915_emit_irq(dev); cookie = i915_emit_irq(dev);
for (i = 0; i < args->buffer_count; i++) { for (i = 0; i < args->buffer_count; i++) {
@ -870,12 +894,13 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
} }
/* Copy the new buffer offsets back to the user's validate list. */ /* Copy the new buffer offsets back to the user's validate list. */
ret = copy_to_user((struct drm_i915_relocation_entry __user*)(uintptr_t) ret = copy_to_user((struct drm_i915_relocation_entry __user *)
args->buffers_ptr, (uintptr_t) args->buffers_ptr,
validate_list, validate_list,
sizeof(*validate_list) * args->buffer_count); sizeof(*validate_list) * args->buffer_count);
if (ret) if (ret)
DRM_ERROR ("failed to copy %d validate entries back to user (%d)\n", DRM_ERROR("failed to copy %d validate entries "
"back to user (%d)\n",
args->buffer_count, ret); args->buffer_count, ret);
err: err:
if (object_list != NULL) { if (object_list != NULL) {
@ -883,7 +908,7 @@ err:
drm_gem_object_unreference(object_list[i]); drm_gem_object_unreference(object_list[i]);
} }
#if 0 #if 1
/* XXX kludge for now as we don't clean the exec ring yet */ /* XXX kludge for now as we don't clean the exec ring yet */
if (object_list != NULL) { if (object_list != NULL) {
for (i = 0; i < args->buffer_count; i++) for (i = 0; i < args->buffer_count; i++)
@ -916,11 +941,12 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
} }
obj_priv = obj->driver_private; obj_priv = obj->driver_private;
if (obj_priv->gtt_space == NULL) if (obj_priv->gtt_space == NULL) {
{ ret = i915_gem_object_bind_to_gtt(obj,
ret = i915_gem_object_bind_to_gtt(obj, (unsigned) args->alignment); (unsigned) args->alignment);
if (ret != 0) { if (ret != 0) {
DRM_ERROR("Failure to bind in i915_gem_pin_ioctl(): %d\n", DRM_ERROR("Failure to bind in "
"i915_gem_pin_ioctl(): %d\n",
ret); ret);
drm_gem_object_unreference(obj); drm_gem_object_unreference(obj);
return ret; return ret;