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radeon: align r600/700 fmask to 128 X blocks. 

After much searching and empricial testing, and reading of
things I've no justifcation for this fix, other than it really
appears this is what the hw is doing or close enough.

It makes sense that each entry in the FMASK corresponds to
an entry in the CMASKm and the CMASK is organised into 128x128
blocks, but I can't find anything in any of the docs/info from AMD.

But I've spent a lot of time on this, and this seems to be the
simplest fix, in that we don't over allocate things too much,
once this fix in place we can nuke the extra multiplier in mesa.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Dave Airlie 2015-01-09 13:34:41 +10:00 committed by Dave Airlie
parent a5003c6f85
commit eca91cf163
1 changed files with 2 additions and 0 deletions
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2
radeon/radeon_surface.c
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@ -366,6 +366,8 @@ static int r6_surface_init_2d(struct radeon_surface_manager *surf_man,
xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) /
(tilew * surf->bpe * surf->nsamples); (tilew * surf->bpe * surf->nsamples);
xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign);
if (surf->flags & RADEON_SURF_FMASK)
xalign = MAX2(128, xalign);
yalign = tilew * surf_man->hw_info.num_pipes; yalign = tilew * surf_man->hw_info.num_pipes;
if (surf->flags & RADEON_SURF_SCANOUT) { if (surf->flags & RADEON_SURF_SCANOUT) {
xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);