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radeon: don't overallocate stencil by 4 on SI and CIK 

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
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Michel Dänzer 2013-11-18 11:40:08 +01:00 committed by Marek Olšák
parent 67d92404d6
commit f0e399d8f0
1 changed files with 3 additions and 2 deletions
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5
radeon/radeon_surface.c
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@ -1436,16 +1436,17 @@ static void si_surf_minify(struct radeon_surface *surf,
*/
if (level == 0 && surf->last_level == 0)
/* Non-mipmap pitch padded to slice alignment */
/* Using just bpe here breaks stencil blitting; surf->bpe works. */
xalign = MAX2(xalign, slice_align / surf->bpe);
else if (surflevel->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
/* Small rows evenly distributed across slice */
xalign = MAX2(xalign, slice_align / surf->bpe / surflevel->nblk_y);
xalign = MAX2(xalign, slice_align / bpe / surflevel->nblk_y);
surflevel->nblk_x = ALIGN(surflevel->nblk_x, xalign);
surflevel->nblk_z = ALIGN(surflevel->nblk_z, zalign);
surflevel->offset = offset;
surflevel->pitch_bytes = surflevel->nblk_x * surf->bpe * surf->nsamples;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
surflevel->slice_size = ALIGN(surflevel->pitch_bytes * surflevel->nblk_y, slice_align);
surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;