amdgpu: add a faster BO list API
Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com>main
Marek Olšák
parent
98cff551b0
commit
f19afaa519
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@ -19,6 +19,8 @@ amdgpu_bo_export
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amdgpu_bo_free
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amdgpu_bo_import
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amdgpu_bo_inc_ref
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amdgpu_bo_list_create_raw
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amdgpu_bo_list_destroy_raw
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amdgpu_bo_list_create
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amdgpu_bo_list_destroy
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amdgpu_bo_list_update
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@ -47,6 +49,7 @@ amdgpu_query_sw_info
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amdgpu_cs_signal_semaphore
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amdgpu_cs_submit
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amdgpu_cs_submit_raw
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amdgpu_cs_submit_raw2
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amdgpu_cs_syncobj_export_sync_file
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amdgpu_cs_syncobj_import_sync_file
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amdgpu_cs_syncobj_reset
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@ -42,6 +42,7 @@ extern "C" {
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#endif
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struct drm_amdgpu_info_hw_ip;
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struct drm_amdgpu_bo_list_entry;
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/*--------------------------------------------------------------------------*/
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/* --------------------------- Defines ------------------------------------ */
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@ -774,6 +775,37 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
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uint64_t timeout_ns,
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bool *buffer_busy);
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/**
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* Creates a BO list handle for command submission.
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*
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* \param dev - \c [in] Device handle.
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* See #amdgpu_device_initialize()
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* \param number_of_buffers - \c [in] Number of BOs in the list
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* \param buffers - \c [in] List of BO handles
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* \param result - \c [out] Created BO list handle
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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* \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2()
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*/
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int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
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uint32_t number_of_buffers,
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struct drm_amdgpu_bo_list_entry *buffers,
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uint32_t *result);
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/**
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* Destroys a BO list handle.
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*
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* \param bo_list - \c [in] BO list handle.
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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* \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()
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*/
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int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list);
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/**
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* Creates a BO list handle for command submission.
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*
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@ -1587,6 +1619,28 @@ int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
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struct drm_amdgpu_cs_chunk *chunks,
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uint64_t *seq_no);
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/**
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* Submit raw command submission to the kernel with a raw BO list handle.
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*
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* \param dev - \c [in] device handle
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* \param context - \c [in] context handle for context id
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* \param bo_list_handle - \c [in] raw bo list handle (0 for none)
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* \param num_chunks - \c [in] number of CS chunks to submit
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* \param chunks - \c [in] array of CS chunks
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* \param seq_no - \c [out] output sequence number for submission.
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*
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* \return 0 on success\n
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* <0 - Negative POSIX Error code
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*
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* \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw()
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*/
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int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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uint32_t bo_list_handle,
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int num_chunks,
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struct drm_amdgpu_cs_chunk *chunks,
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uint64_t *seq_no);
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void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
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struct drm_amdgpu_cs_chunk_dep *dep);
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void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
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@ -618,6 +618,40 @@ out:
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return r;
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}
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drm_public int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
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uint32_t number_of_buffers,
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struct drm_amdgpu_bo_list_entry *buffers,
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uint32_t *result)
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{
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union drm_amdgpu_bo_list args;
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int r;
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memset(&args, 0, sizeof(args));
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args.in.operation = AMDGPU_BO_LIST_OP_CREATE;
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args.in.bo_number = number_of_buffers;
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args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
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args.in.bo_info_ptr = (uint64_t)(uintptr_t)buffers;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
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&args, sizeof(args));
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if (!r)
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*result = args.out.list_handle;
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return r;
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}
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drm_public int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev,
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uint32_t bo_list)
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{
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union drm_amdgpu_bo_list args;
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memset(&args, 0, sizeof(args));
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args.in.operation = AMDGPU_BO_LIST_OP_DESTROY;
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args.in.list_handle = bo_list;
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return drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
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&args, sizeof(args));
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}
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drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev,
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uint32_t number_of_resources,
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amdgpu_bo_handle *resources,
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@ -731,6 +731,31 @@ drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
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return 0;
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}
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drm_public int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
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amdgpu_context_handle context,
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uint32_t bo_list_handle,
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int num_chunks,
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struct drm_amdgpu_cs_chunk *chunks,
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uint64_t *seq_no)
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{
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union drm_amdgpu_cs cs = {0};
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uint64_t *chunk_array;
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int i, r;
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chunk_array = alloca(sizeof(uint64_t) * num_chunks);
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for (i = 0; i < num_chunks; i++)
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chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
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cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
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cs.in.ctx_id = context->id;
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cs.in.bo_list_handle = bo_list_handle;
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cs.in.num_chunks = num_chunks;
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r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
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&cs, sizeof(cs));
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if (!r && seq_no)
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*seq_no = cs.out.handle;
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return r;
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}
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drm_public void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
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struct drm_amdgpu_cs_chunk_data *data)
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{
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