From f1b897ec8371f999abc9cc4fa087e34ab9e11899 Mon Sep 17 00:00:00 2001
From: Flora Cui <flora.cui@amd.com>
Date: Thu, 7 Jul 2022 21:01:56 +0800
Subject: [PATCH] tests/amdgpu: add dispatch/draw test for gfx11

Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
 tests/amdgpu/shader_code.h       |   9 +
 tests/amdgpu/shader_code_gfx11.h | 320 ++++++++++++++++++++++
 tests/amdgpu/shader_test_util.c  | 437 ++++++++++++++++++++++++++++++-
 3 files changed, 764 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/shader_code_gfx11.h

diff --git a/tests/amdgpu/shader_code.h b/tests/amdgpu/shader_code.h
index 8f9357b4..74d32bb5 100644
--- a/tests/amdgpu/shader_code.h
+++ b/tests/amdgpu/shader_code.h
@@ -31,6 +31,7 @@
 enum amdgpu_test_gfx_version {
 	AMDGPU_TEST_GFX_V9 = 0,
 	AMDGPU_TEST_GFX_V10,
+	AMDGPU_TEST_GFX_V11,
 	AMDGPU_TEST_GFX_MAX,
 };
 
@@ -60,6 +61,7 @@ struct reg_info {
 #include "shader_code_hang.h"
 #include "shader_code_gfx9.h"
 #include "shader_code_gfx10.h"
+#include "shader_code_gfx11.h"
 
 struct shader_test_cs_shader {
 	const uint32_t *shader;
@@ -100,6 +102,10 @@ static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2]
 	{{bufferclear_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
 	// gfx10, cs_buffercopy
 	{buffercopy_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
+	// gfx11, cs_bufferclear
+	{{bufferclear_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)},
+	// gfx11, cs_buffercopy
+	{buffercopy_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)}},
 };
 
 #define SHADER_PS_INFO(_ps, _n) \
@@ -112,6 +118,7 @@ static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2]
 static const struct shader_test_ps_shader shader_test_ps[AMDGPU_TEST_GFX_MAX][2] = {
 	{SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)},
 	{SHADER_PS_INFO(const, 10), SHADER_PS_INFO(tex, 10)},
+	{SHADER_PS_INFO(const, 11), SHADER_PS_INFO(tex, 11)},
 };
 
 #define SHADER_VS_INFO(_vs, _n) \
@@ -121,6 +128,7 @@ static const struct shader_test_ps_shader shader_test_ps[AMDGPU_TEST_GFX_MAX][2]
 static const struct shader_test_vs_shader shader_test_vs[AMDGPU_TEST_GFX_MAX][1] = {
 	{SHADER_VS_INFO(RectPosTexFast, 9)},
 	{SHADER_VS_INFO(RectPosTexFast, 10)},
+	{SHADER_VS_INFO(RectPosTexFast, 11)},
 };
 
 struct shader_test_gfx_info {
@@ -140,5 +148,6 @@ struct shader_test_gfx_info {
 static struct shader_test_gfx_info shader_test_gfx_info[AMDGPU_TEST_GFX_MAX] = {
 	{SHADER_TEST_GFX_INFO(9),},
 	{SHADER_TEST_GFX_INFO(10),},
+	{SHADER_TEST_GFX_INFO(11),},
 };
 #endif
diff --git a/tests/amdgpu/shader_code_gfx11.h b/tests/amdgpu/shader_code_gfx11.h
new file mode 100644
index 00000000..d9ee0a7c
--- /dev/null
+++ b/tests/amdgpu/shader_code_gfx11.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifndef _shader_code_gfx11_h_
+#define _shader_code_gfx11_h_
+
+static const uint32_t bufferclear_cs_shader_gfx11[] = {
+	0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF,
+	0x7E020205, 0x7E040206, 0x7E060207, 0xBF870004,
+	0xD6460004, 0x04010C08, 0x7E000204, 0xE01C0000,
+	0x80800004, 0xBFB60003, 0xBFB00000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000
+};
+
+static const struct reg_info bufferclear_cs_shader_registers_gfx11[] = {
+	{0x2e12, 0x600C0041},	//{ mmCOMPUTE_PGM_RSRC1,	  0x600C0041 },
+	{0x2e13, 0x00000090},	//{ mmCOMPUTE_PGM_RSRC2,	  0x00000090 },
+	{0x2e07, 0x00000040},	//{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
+	{0x2e08, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
+	{0x2e09, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
+};
+
+static const uint32_t buffercopy_cs_shader_gfx11[] = {
+	0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF,
+	0xBF870001, 0xD6460001, 0x04010C08, 0xE00C0000,
+	0x80800201, 0xBF8903F7, 0xE01C0000, 0x80810201,
+	0xBFB60003, 0xBFB00000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000
+};
+
+static const uint32_t ps_const_shader_gfx11[] = {
+    0xB0802006, 0xBF840003, 0x7E000200, 0x7E020201,
+    0x7E040202, 0x7E060203, 0x5E000300, 0x5E020702,
+    0xBF800000, 0xBF800000, 0xF8000803, 0x00000100,
+    0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000
+};
+
+static const uint32_t ps_const_shader_patchinfo_code_size_gfx11 = 6;
+
+static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = {
+	{{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 },  // SI_EXPORT_FMT_ZERO
+	{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 },  // SI_EXPORT_FMT_32_R
+	{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_32_GR
+	{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 },  // SI_EXPORT_FMT_32_AR
+	{ 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_FP16_ABGR
+	{ 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_UNORM16_ABGR
+	{ 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_SNORM16_ABGR
+	{ 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_uint32_t16_ABGR
+	{ 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_SINT16_ABGR
+	{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 }   // SI_EXPORT_FMT_32_ABGR
+	}
+};
+
+static const uint32_t ps_const_shader_patchinfo_offset_gfx11[] = {
+	0x00000006
+};
+
+static const uint32_t ps_const_num_sh_registers_gfx11 = 2;
+
+static const struct reg_info ps_const_sh_registers_gfx11[] = {
+	{0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 },
+	{0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
+};
+
+static const struct reg_info ps_const_context_registers_gfx11[] = {
+	{0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
+	{0xA1B6, 0x00000000 }, //{ mmSPI_PS_IN_CONTROL,       0x00000000 },
+	{0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK,          0x0000000F },
+	{0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL,       0x00000010 },
+	{0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
+	{0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
+	{0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
+};
+
+static const uint32_t ps_const_num_context_registers_gfx11 = 7;
+
+static const uint32_t ps_tex_shader_gfx11[] =
+{
+    0xB0802006, 0xBF840003, 0xBEFD000C, 0xBE8E017E,
+    0xBEFE1D7E, 0xCE000003, 0xCE000102, 0xCD000104,
+    0x040E0103, 0xCD000000, 0x040A0102, 0xBF870112,
+    0xCD010703, 0x04120303, 0xCD010700, 0x04020302,
+    0x8BFE0E7E, 0xF06C0F05, 0x08000003, 0x00000000,
+    0xBEFE010E, 0xBF8903F7, 0x5E000300, 0x5E020702,
+    0xBF800000, 0xBF800000, 0xF8000803, 0x00000100,
+    0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+    0xBF9F0000
+};
+
+static const uint32_t ps_tex_shader_patchinfo_offset_gfx11[] =
+{
+    0x00000016
+};
+
+// Denotes the Patch Info Code Length
+static const uint32_t ps_tex_shader_patchinfo_code_size_gfx11 = 6;
+
+static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] =
+{
+    {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 },  // SI_EXPORT_FMT_ZERO
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 },  // SI_EXPORT_FMT_32_R
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_32_GR
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 },  // SI_EXPORT_FMT_32_AR
+     { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_FP16_ABGR
+     { 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_UNORM16_ABGR
+     { 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_SNORM16_ABGR
+     { 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_uint32_t16_ABGR
+     { 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 },  // SI_EXPORT_FMT_SINT16_ABGR
+     { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 }   // SI_EXPORT_FMT_32_ABGR
+    }
+};
+// Holds Sh Register Information
+static const struct reg_info ps_tex_sh_registers_gfx11[] =
+{
+    {0x2C0A, 0x020C0081 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0081 },
+    {0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
+};
+
+static const uint32_t ps_tex_num_sh_registers_gfx11 = 2;
+
+// Holds Context Register Information
+static const struct reg_info ps_tex_context_registers_gfx11[] =
+{
+    {0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR,       0x00000002 },
+    {0xA1B6, 0x00000001 }, //{ mmSPI_PS_IN_CONTROL,       0x00000001 },
+    {0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK,          0x0000000F },
+    {0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL,       0x00000010 },
+    {0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT,     0x00000000 },
+    {0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL,          0x00000000 /* Always 0 for now */},
+    {0xA1C5, 0x00000004 } //{ mmSPI_SHADER_COL_FORMAT,   0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ }
+};
+
+static const uint32_t ps_tex_num_context_registers_gfx11 = 7;
+
+
+static const uint32_t vs_RectPosTexFast_shader_gfx11[] =
+{
+	0xB0802006, 0xBEFE01C1, 0xBF840003, 0xF408050A,
+	0xF80000B0, 0xD71F0001, 0x000100C1, 0x9300FF03,
+	0x00040018, 0x9301FF02, 0x0009000C, 0xBF870091,
+	0xD7200001, 0x000202C1, 0xD60B0001, 0x04058000,
+	0xBF870001, 0xD4490000, 0x00000301, 0xBE862100,
+	0x7E040B05, 0xBFA5001C, 0x7E06020A, 0x7E08020E,
+	0x7E0A020F, 0xBF8701B4, 0x060404F3, 0x7E140211,
+	0x7E0E0210, 0x7C240480, 0x060404F3, 0xD5010003,
+	0x01AA0608, 0xD5010004, 0x01AA080C, 0xBF870003,
+	0xD4120012, 0x00010102, 0x7E04020B, 0xBEEA1F12,
+	0xBF870483, 0xD5010008, 0x01AA080C, 0xD5010006,
+	0x01AA0608, 0xBF870003, 0xD5010004, 0x004A0409,
+	0xD5010009, 0x004A0A0D, 0xBEFE0106, 0x9302FF02,
+	0x00090016, 0xBF870009, 0xD4C9007E, 0x00000501,
+	0xBFA50002, 0xF8000941, 0x00000000, 0xBF89FFF0,
+	0x8BFE0006, 0xD71F0000, 0x000100C1, 0xBFA50013,
+	0x7E1602F2, 0x9300FF03, 0x00040018, 0x8B01FF05,
+	0x00007FFF, 0xBF8704B2, 0xD7200000, 0x000200C1,
+	0x7E0202F2, 0x84018901, 0x80018001, 0xBF870002,
+	0xD60B0000, 0x04018000, 0xF80008CF, 0x01070406,
+	0xBF89FC07, 0xE0744000, 0x01850800, 0xBFB00000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000,
+	0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000
+};
+
+static const struct reg_info vs_RectPosTexFast_sh_registers_gfx11[] =
+{
+	{0x2C8A, 0x020C00C2}, //{ mmSPI_SHADER_PGM_RSRC1_GS, 0x020C00C2 },
+	{0x2C8B, 0x0008001C}, //{ mmSPI_SHADER_PGM_RSRC2_GS, 0x0008001C }
+};
+
+static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx11 = 2;
+
+// Holds Context Register Information
+static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] =
+{
+	{0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 },
+	{0xA1C2, 0x00000001}, //{ mmSPI_SHADER_IDX_FORMAT, 0x00000001 },
+	{0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */},
+	{0xA2E4, 0x00000000}, //{ mmVGT_GS_INSTANCE_CNT, 0x00000000 },
+	{0xA2AB, 0x00000004}, //{ mmVGT_ESGS_RING_ITEMSIZE, 0x00000004 },
+	{0xA2CE, 0x00000001}, //{ mmVGT_GS_MAX_VERT_OUT, 0x00000001 }
+};
+
+static const uint32_t vs_RectPosTexFast_num_context_registers_gfx11 = 6;
+
+static const uint32_t preamblecache_gfx11[] = {
+	0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
+	0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94,  0x80000000, 0x40004000,
+	0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, 0xc0016900, 0x208, 0x0,
+	0xc0016900, 0x2a1, 0x0, 0xc0016900,  0x2ad, 0x0, 0xc0016900, 0x2dc, 0x0,
+	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000,  0x3f800000,
+	0xc0046900, 0x310, 0x0, 0x3, 0x0, 0x100000, 0xc0016900, 0x349, 0x0,
+	0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, 0xc0016900, 0x376,  0x0,
+	0xc0016900, 0x385, 0x0, 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+	0xc0026900, 0x204, 0x90000, 0x4, 0xc0016900, 0x20c, 0x0,  0xc0026900, 0x20e, 0x0, 0x0,
+	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
+	0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0x0,  0xc0016900, 0x2a6, 0x0,
+	0xc0016900, 0x210, 0x0, 0xc0016900, 0x2db, 0x0, 0xc0016900, 0x2e4, 0x0,
+	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x0, 0xc0016900,  0x206, 0x300,
+	0xc0016900, 0x212, 0x200, 0xc0016900, 0xf4, 0x0, 0xc0016900, 0x18, 0x0,
+	0xc0016900, 0x1d4, 0xff, 0xc0016900, 0x2ce, 0x1, 0xc0016900, 0x2d3, 0x20001,
+	0xc0016900, 0x1ff, 0x80,  0xc0016900, 0x2d5, 0x6012010, 0xc0017a00, 0x20000243, 0x0,
+	0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0, 0xc0017900, 0x24b, 0x0,
+	0xc0017900,  0x259, 0xffffffff, 0xc0017900, 0x25f, 0x0, 0xc0017900, 0x260, 0x0,
+	0xc0017900, 0x262, 0x0, 0xc0017900, 0x444, 0x0, 0xc0017900, 0x445, 0x0,
+	0xc0017600, 0x6, 0x0, 0xc0017600, 0x80, 0x0, 0xc0017600, 0xb0, 0x0,
+	0xc0047600, 0xb2, 0x0, 0x0, 0x0, 0x0, 0xc0017600, 0x30, 0x0,
+	0xc0047600, 0x32, 0x0, 0x0, 0x0, 0x0
+};
+
+static const uint32_t cached_cmd_gfx11[] = {
+	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
+	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
+	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
+	0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x0,
+	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
+	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
+	0xc0026900, 0x292, 0x20, 0x6020000,
+	0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0,
+	0xc0046900, 0x1d5, 0x0, 0x0, 0x0, 0x0, 0xc0016900, 0x104, 0x4a00005,
+	0xc0016900, 0x1f, 0xf2a0055, 0xc0017900, 0x266, 0x4
+};
+static const uint32_t sh_reg_base_gfx11 = 0x2C00;
+static const uint32_t context_reg_base_gfx11 = 0xA000;
+
+#endif
diff --git a/tests/amdgpu/shader_test_util.c b/tests/amdgpu/shader_test_util.c
index bf62efbe..60148fb8 100644
--- a/tests/amdgpu/shader_test_util.c
+++ b/tests/amdgpu/shader_test_util.c
@@ -62,6 +62,7 @@ struct shader_test_priv {
 		struct shader_test_draw shader_draw;
 		struct shader_test_dispatch shader_dispatch;
 	};
+	struct shader_test_bo vtx_attributes_mem;
 	struct shader_test_bo cmd;
 	struct shader_test_bo src;
 	struct shader_test_bo dst;
@@ -106,6 +107,9 @@ void shader_test_for_each(amdgpu_device_handle device_handle, unsigned ip,
 	case 10:
 		test_info.version = AMDGPU_TEST_GFX_V10;
 		break;
+	case 11:
+		test_info.version = AMDGPU_TEST_GFX_V11;
+		break;
 	default:
 		printf("SKIP ... unsupported gfx version %d\n", info.hw_ip_version_major);
 		return;
@@ -248,6 +252,45 @@ static void amdgpu_dispatch_init_gfx10(struct shader_test_priv *test_priv)
 	test_priv->cmd_curr = i;
 }
 
+static void amdgpu_dispatch_init_gfx11(struct shader_test_priv *test_priv)
+{
+	int i;
+	uint32_t *ptr = test_priv->cmd.ptr;
+
+	/* Write context control and load shadowing register if necessary */
+	write_context_control(test_priv);
+
+	i = test_priv->cmd_curr;
+
+	/* Issue commands to set default compute state. */
+	/* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */
+	ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 3);
+	ptr[i++] = 0x204;
+	i += 3;
+
+	/* clear mmCOMPUTE_TMPRING_SIZE */
+	ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
+	ptr[i++] = 0x218;
+	ptr[i++] = 0;
+
+	/* mmCOMPUTE_REQ_CTRL */
+	ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
+	ptr[i++] = 0x222;
+	ptr[i++] = 0;
+
+	/* mmCOMPUTE_USER_ACCUM_0 .. 3*/
+	ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
+	ptr[i++] = 0x224;
+	i += 4;
+
+	/* mmCOMPUTE_SHADER_CHKSUM */
+	ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+	ptr[i++] = 0x22a;
+	ptr[i++] = 0;
+
+	test_priv->cmd_curr = i;
+}
+
 static void amdgpu_dispatch_init(struct shader_test_priv *test_priv)
 {
 	switch (test_priv->info->version) {
@@ -257,6 +300,9 @@ static void amdgpu_dispatch_init(struct shader_test_priv *test_priv)
 	case AMDGPU_TEST_GFX_V10:
 		amdgpu_dispatch_init_gfx10(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_V11:
+		amdgpu_dispatch_init_gfx11(test_priv);
+		break;
 	}
 }
 
@@ -280,6 +326,7 @@ static void amdgpu_dispatch_write_cumask(struct shader_test_priv *test_priv)
 		ptr[i++] = 0xffffffff;
 		break;
 	case AMDGPU_TEST_GFX_V10:
+	case AMDGPU_TEST_GFX_V11:
 		/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
 		ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG_INDEX, 2);
 		ptr[i++] = 0x30000216;
@@ -415,6 +462,73 @@ static void amdgpu_dispatch_write2hw_gfx10(struct shader_test_priv *test_priv)
 	test_priv->cmd_curr = i;
 }
 
+static void amdgpu_dispatch_write2hw_gfx11(struct shader_test_priv *test_priv)
+{
+	enum amdgpu_test_gfx_version version = test_priv->info->version;
+	const struct shader_test_cs_shader *cs_shader = &shader_test_cs[version][test_priv->shader_dispatch.cs_type];
+	int j, i = test_priv->cmd_curr;
+	uint32_t *ptr = test_priv->cmd.ptr;
+	uint64_t shader_addr = test_priv->shader_dispatch.cs_bo.mc_address;
+
+	/* Writes shader state to HW */
+	/* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */
+	ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2);
+	ptr[i++] = 0x20c;
+	ptr[i++] = (shader_addr >> 8);
+	ptr[i++] = (shader_addr >> 40);
+
+	/* write sh regs*/
+	for (j = 0; j < cs_shader->num_sh_reg; j++) {
+		ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
+		/* - Gfx9ShRegBase */
+		ptr[i++] = cs_shader->sh_reg[j].reg_offset - shader_test_gfx_info[version].sh_reg_base;
+		ptr[i++] = cs_shader->sh_reg[j].reg_value;
+		if (cs_shader->sh_reg[j].reg_offset == 0x2E12)
+			ptr[i-1] &= ~(1<<29);
+	}
+
+	/* mmCOMPUTE_PGM_RSRC3 */
+	ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1);
+	ptr[i++] = 0x228;
+	ptr[i++] = 0x3f0;
+
+	/* Write constant data */
+	/* Writes the texture resource constants data to the SGPRs */
+	if (CS_BUFFERCLEAR == test_priv->shader_dispatch.cs_type) {
+		ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
+		ptr[i++] = 0x240;
+		ptr[i++] = test_priv->dst.mc_address;
+		ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000;
+		ptr[i++] = test_priv->dst.size / 16;
+		ptr[i++] = 0x1003dfac;
+
+		/* Sets a range of pixel shader constants */
+		ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
+		ptr[i++] = 0x244;
+		ptr[i++] = 0x22222222;
+		ptr[i++] = 0x22222222;
+		ptr[i++] = 0x22222222;
+		ptr[i++] = 0x22222222;
+	} else {
+		ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
+		ptr[i++] = 0x240;
+		ptr[i++] = test_priv->src.mc_address;
+		ptr[i++] = (test_priv->src.mc_address >> 32) | 0x100000;
+		ptr[i++] = test_priv->src.size / 16;
+		ptr[i++] = 0x1003dfac;
+
+		/* Writes the UAV constant data to the SGPRs. */
+		ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4);
+		ptr[i++] = 0x244;
+		ptr[i++] = test_priv->dst.mc_address;
+		ptr[i++] = (test_priv->dst.mc_address>> 32) | 0x100000;
+		ptr[i++] = test_priv->dst.size / 16;
+		ptr[i++] = 0x1003dfac;
+	}
+
+	test_priv->cmd_curr = i;
+}
+
 static void amdgpu_dispatch_write2hw(struct shader_test_priv *test_priv)
 {
 	switch (test_priv->info->version) {
@@ -424,6 +538,9 @@ static void amdgpu_dispatch_write2hw(struct shader_test_priv *test_priv)
 	case AMDGPU_TEST_GFX_V10:
 		amdgpu_dispatch_write2hw_gfx10(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_V11:
+		amdgpu_dispatch_write2hw_gfx11(test_priv);
+		break;
 	}
 }
 
@@ -830,6 +947,15 @@ static void amdgpu_draw_init(struct shader_test_priv *test_priv)
 	write_context_control(test_priv);
 	i = test_priv->cmd_curr;
 
+	if (test_priv->info->version == AMDGPU_TEST_GFX_V11) {
+		ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+		ptr[i++] = 0x446;
+		ptr[i++] = (test_priv->vtx_attributes_mem.mc_address >> 16);
+		// mmSPI_ATTRIBUTE_RING_SIZE
+		ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+		ptr[i++] = 0x447;
+		ptr[i++] = 0x20001;
+	}
 	memcpy(ptr + i, gfx_info->preamble_cache, gfx_info->size_preamble_cache);
 
 	test_priv->cmd_curr = i + gfx_info->size_preamble_cache/sizeof(uint32_t);
@@ -976,6 +1102,60 @@ static void amdgpu_draw_setup_and_write_drawblt_surf_info_gfx10(struct shader_te
 	test_priv->cmd_curr = i;
 }
 
+static void amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(struct shader_test_priv *test_priv)
+{
+	int i = test_priv->cmd_curr;
+	uint32_t *ptr = test_priv->cmd.ptr;
+
+	/* mmCB_COLOR0_BASE */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x318;
+	ptr[i++] = test_priv->dst.mc_address >> 8;
+	/* mmCB_COLOR0_VIEW .. mmCB_COLOR0_DCC_CONTROL */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 4);
+	ptr[i++] = 0x31b;
+	i++;
+	ptr[i++] = 0x5040e;
+	i += 2;
+	/* mmCB_COLOR0_DCC_BASE */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x325;
+	ptr[i++] = 0;
+	/* mmCB_COLOR0_BASE_EXT */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x390;
+	ptr[i++] = (test_priv->dst.mc_address >> 40) & 0xFF;
+	/* mmCB_COLOR0_DCC_BASE_EXT */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x3a8;
+	ptr[i++] = 0;
+	/* mmCB_COLOR0_ATTRIB2 */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x3b0;
+	ptr[i++] = test_priv->info->hang_slow ? 0x1ffc7ff : 0x7c01f;
+	/* mmCB_COLOR0_ATTRIB3 */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x3b8;
+	ptr[i++] = test_priv->info->hang_slow ? 0x1028000 : 0x1018000;
+	/* mmCB_COLOR0_INFO */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x32b;
+	ptr[i++] = 0;
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x33a;
+	ptr[i++] = 0;
+	/* mmSPI_SHADER_COL_FORMAT */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x1c5;
+	ptr[i++] = 0x9;
+	/* mmDB_Z_INFO */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
+	ptr[i++] = 0x10;
+	i += 2;
+
+	test_priv->cmd_curr = i;
+}
+
 static void amdgpu_draw_setup_and_write_drawblt_surf_info(struct shader_test_priv *test_priv)
 {
 	switch (test_priv->info->version) {
@@ -985,6 +1165,9 @@ static void amdgpu_draw_setup_and_write_drawblt_surf_info(struct shader_test_pri
 	case AMDGPU_TEST_GFX_V10:
 		amdgpu_draw_setup_and_write_drawblt_surf_info_gfx10(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_V11:
+		amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(test_priv);
+		break;
 	}
 }
 
@@ -1068,6 +1251,41 @@ static void amdgpu_draw_setup_and_write_drawblt_state_gfx10(struct shader_test_p
 	test_priv->cmd_curr = i;
 }
 
+static void amdgpu_draw_setup_and_write_drawblt_state_gfx11(struct shader_test_priv *test_priv)
+{
+	int i = test_priv->cmd_curr;
+	uint32_t *ptr = test_priv->cmd.ptr;
+	const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version];
+
+	/* mmPA_SC_TILE_STEERING_OVERRIDE */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0xd7;
+	ptr[i++] = 0;
+
+	ptr[i++] = 0xffff1000;
+	ptr[i++] = 0xc0021000;
+
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0xd7;
+	i++;
+
+	/* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16);
+	ptr[i++] = 0x2fe;
+	i += 16;
+
+	/* mmPA_SC_CENTROID_PRIORITY_0 */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
+	ptr[i++] = 0x2f5;
+	i += 2;
+
+	memcpy(ptr + i, gfx_info->cached_cmd, gfx_info->size_cached_cmd);
+	if (test_priv->info->hang_slow)
+		*(ptr + i + 12) = 0x8000800;
+
+	test_priv->cmd_curr = i + gfx_info->size_cached_cmd/sizeof(uint32_t);
+}
+
 static void amdgpu_draw_setup_and_write_drawblt_state(struct shader_test_priv *test_priv)
 {
 	switch (test_priv->info->version) {
@@ -1077,6 +1295,9 @@ static void amdgpu_draw_setup_and_write_drawblt_state(struct shader_test_priv *t
 	case AMDGPU_TEST_GFX_V10:
 		amdgpu_draw_setup_and_write_drawblt_state_gfx10(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_V11:
+		amdgpu_draw_setup_and_write_drawblt_state_gfx11(test_priv);
+		break;
 	}
 }
 
@@ -1215,6 +1436,104 @@ static void amdgpu_draw_vs_RectPosTexFast_write2hw_gfx10(struct shader_test_priv
 	test_priv->cmd_curr = i;
 }
 
+
+static void amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(struct shader_test_priv *test_priv)
+{
+	int i = test_priv->cmd_curr;
+	uint32_t *ptr = test_priv->cmd.ptr;
+	const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version];
+	uint64_t shader_addr = test_priv->shader_draw.vs_bo.mc_address;
+	const struct shader_test_vs_shader *shader = &shader_test_vs[test_priv->info->version][test_priv->shader_draw.vs_type];
+	enum ps_type ps = test_priv->shader_draw.ps_type;
+	int j, offset;
+
+	/* mmPA_CL_VS_OUT_CNTL */
+	ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+	ptr[i++] = 0x207;
+	ptr[i++] = 0;
+
+	/* mmSPI_SHADER_PGM_RSRC3_GS */
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
+	ptr[i++] = 0x30000087;
+	ptr[i++] = 0xffff;
+	/* mmSPI_SHADER_PGM_RSRC4_GS */
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
+	ptr[i++] = 0x30000081;
+	ptr[i++] = 0x1fff0001;
+
+	/* mmSPI_SHADER_PGM_LO_ES */
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2);
+	ptr[i++] = 0xc8;
+	ptr[i++] = shader_addr >> 8;
+	ptr[i++] = shader_addr >> 40;
+
+	/* write sh reg */
+	for (j = 0; j < shader->num_sh_reg; j++) {
+		ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
+		ptr[i++] = shader->sh_reg[j].reg_offset - gfx_info->sh_reg_base;
+		ptr[i++] = shader->sh_reg[j].reg_value;
+	}
+	/* write context reg */
+	for (j = 0; j < shader->num_context_reg; j++) {
+		switch (shader->context_reg[j].reg_offset) {
+		case 0xA1B1: //mmSPI_VS_OUT_CONFIG
+			ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+			ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base;
+			ptr[i++] = 2;
+			break;
+		case 0xA1C3: //mmSPI_SHADER_POS_FORMAT
+			ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+			ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base;
+			ptr[i++] = 4;
+			break;
+		case 0xA2E4: //mmVGT_GS_INSTANCE_CNT
+		case 0xA2CE: //mmVGT_GS_MAX_VERT_OUT
+			break;
+		default:
+			ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+			ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base;
+			ptr[i++] = shader->context_reg[j].reg_value;
+			break;
+		}
+	}
+
+	// write constant
+	// dst rect
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
+	ptr[i++] = 0x8c;
+	i += 2;
+	ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000;
+	ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000;
+	// src rect
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
+	ptr[i++] = 0x90;
+	i += 2;
+	if (ps == PS_CONST) {
+		i += 2;
+	} else if (ps == PS_TEX) {
+		ptr[i++] = 0x3f800000;
+		ptr[i++] = 0x3f800000;
+	}
+
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
+	ptr[i++] = 0x94;
+	i += 4;
+	// vtx_attributes_mem
+	ptr[i++] = 0xc02f1000;
+	offset = i * sizeof(uint32_t);
+	i += 44;
+	ptr[i++] = test_priv->vtx_attributes_mem.mc_address & 0xffffffff;
+	ptr[i++] = 0xc0100000 | ((test_priv->vtx_attributes_mem.mc_address >> 32) & 0xffff);
+	ptr[i++] = test_priv->vtx_attributes_mem.size / 16;
+	ptr[i++] = 0x2043ffac;
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG_OFFSET, 2);
+	ptr[i++] = 0x98;
+	ptr[i++] = offset;
+	i++;
+
+	test_priv->cmd_curr = i;
+}
+
 static void amdgpu_draw_vs_RectPosTexFast_write2hw(struct shader_test_priv *test_priv)
 {
 	switch (test_priv->info->version) {
@@ -1224,6 +1543,9 @@ static void amdgpu_draw_vs_RectPosTexFast_write2hw(struct shader_test_priv *test
 	case AMDGPU_TEST_GFX_V10:
 		amdgpu_draw_vs_RectPosTexFast_write2hw_gfx10(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_V11:
+		amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(test_priv);
+		break;
 	}
 }
 
@@ -1291,6 +1613,62 @@ static void amdgpu_draw_ps_write2hw_gfx9_10(struct shader_test_priv *test_priv)
 	test_priv->cmd_curr = i;
 }
 
+static void amdgpu_draw_ps_write2hw_gfx11(struct shader_test_priv *test_priv)
+{
+	int i, j;
+	uint64_t shader_addr = test_priv->shader_draw.ps_bo.mc_address;
+	enum amdgpu_test_gfx_version version = test_priv->info->version;
+	const struct shader_test_ps_shader *ps = &shader_test_ps[version][test_priv->shader_draw.ps_type];
+	uint32_t *ptr = test_priv->cmd.ptr;
+	uint32_t export_shader_offset;
+
+	i = test_priv->cmd_curr;
+
+	/* SPI_SHADER_PGM_LO_PS
+	   SPI_SHADER_PGM_HI_PS */
+	shader_addr >>= 8;
+	if (!test_priv->info->hang) {
+		export_shader_offset = (round_up_size(ps->shader_size) * 9) >> 8;
+		shader_addr += export_shader_offset;
+	}
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2);
+	ptr[i++] = 0x8;
+	ptr[i++] = shader_addr & 0xffffffff;
+	ptr[i++] = (shader_addr >> 32) & 0xffffffff;
+	/* mmSPI_SHADER_PGM_RSRC3_PS */
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
+	ptr[i++] = 0x30000007;
+	ptr[i++] = 0xffff;
+	/* mmSPI_SHADER_PGM_RSRC4_PS */
+	ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1);
+	ptr[i++] = 0x30000001;
+	ptr[i++] = 0x3fffff;
+
+	for (j = 0; j < ps->num_sh_reg; j++) {
+		ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1);
+		ptr[i++] = ps->sh_reg[j].reg_offset - shader_test_gfx_info[version].sh_reg_base;
+		ptr[i++] = ps->sh_reg[j].reg_value;
+	}
+
+	for (j = 0; j < ps->num_context_reg; j++) {
+		/* !mmSPI_SHADER_COL_FORMAT */
+		if (ps->context_reg[j].reg_offset != 0xA1C5) {
+			ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+			ptr[i++] = ps->context_reg[j].reg_offset - shader_test_gfx_info[version].context_reg_base;
+			ptr[i++] = ps->context_reg[j].reg_value;
+		}
+
+		/* mmSPI_PS_INPUT_ADDR */
+		if (ps->context_reg[j].reg_offset == 0xA1B4) {
+			ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
+			ptr[i++] = 0x1b3;
+			ptr[i++] = 2;
+		}
+	}
+
+	test_priv->cmd_curr = i;
+}
+
 static void amdgpu_draw_ps_write2hw(struct shader_test_priv *test_priv)
 {
 	switch (test_priv->info->version) {
@@ -1298,6 +1676,9 @@ static void amdgpu_draw_ps_write2hw(struct shader_test_priv *test_priv)
 	case AMDGPU_TEST_GFX_V10:
 		amdgpu_draw_ps_write2hw_gfx9_10(test_priv);
 		break;
+	case AMDGPU_TEST_GFX_V11:
+		amdgpu_draw_ps_write2hw_gfx11(test_priv);
+		break;
 	}
 }
 
@@ -1327,6 +1708,16 @@ static void amdgpu_draw_draw(struct shader_test_priv *test_priv)
 		ptr[i++] = 0x242;
 		ptr[i++] = 0x11;
 		break;
+	case AMDGPU_TEST_GFX_V11:
+		/* mmGE_CNTL */
+		ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+		ptr[i++] = 0x25b;
+		ptr[i++] = 0x80fc80;
+		/* mmVGT_PRIMITIVE_TYPE */
+		ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+		ptr[i++] = 0x242;
+		ptr[i++] = 0x11;
+		break;
 	}
 
 	ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
@@ -1344,7 +1735,8 @@ static void amdgpu_memset_draw_test(struct shader_test_info *test_info)
 	struct shader_test_bo *vs_bo = &(test_priv.shader_draw.vs_bo);
 	struct shader_test_bo *dst = &(test_priv.dst);
 	struct shader_test_bo *cmd = &(test_priv.cmd);
-	amdgpu_bo_handle resources[4];
+	struct shader_test_bo *vtx_attributes_mem = &(test_priv.vtx_attributes_mem);
+	amdgpu_bo_handle resources[5];
 	uint8_t *ptr_dst;
 	uint32_t *ptr_cmd;
 	int i, r;
@@ -1391,6 +1783,14 @@ static void amdgpu_memset_draw_test(struct shader_test_info *test_info)
 	r = shader_test_bo_alloc(test_info->device_handle, dst);
 	CU_ASSERT_EQUAL(r, 0);
 
+	if (test_info->version == AMDGPU_TEST_GFX_V11) {
+		vtx_attributes_mem->size = 0x4040000;
+		vtx_attributes_mem->heap = AMDGPU_GEM_DOMAIN_VRAM;
+
+		r = shader_test_bo_alloc(test_info->device_handle, vtx_attributes_mem);
+		CU_ASSERT_EQUAL(r, 0);
+	}
+
 	amdgpu_draw_init(&test_priv);
 
 	amdgpu_draw_setup_and_write_drawblt_surf_info(&test_priv);
@@ -1423,6 +1823,8 @@ static void amdgpu_memset_draw_test(struct shader_test_info *test_info)
 	resources[i++] = ps_bo->bo;
 	resources[i++] = vs_bo->bo;
 	resources[i++] = cmd->bo;
+	if (vtx_attributes_mem->size)
+		resources[i++] = vtx_attributes_mem->bo;
 	r = amdgpu_bo_list_create(test_info->device_handle, i, resources, NULL, &bo_list);
 	CU_ASSERT_EQUAL(r, 0);
 
@@ -1465,6 +1867,11 @@ static void amdgpu_memset_draw_test(struct shader_test_info *test_info)
 	i = dst->size / 2;
 	CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0);
 
+	if (vtx_attributes_mem->size) {
+		r = shader_test_bo_free(vtx_attributes_mem);
+		CU_ASSERT_EQUAL(r, 0);
+	}
+
 	r = shader_test_bo_free(dst);
 	CU_ASSERT_EQUAL(r, 0);
 
@@ -1490,7 +1897,8 @@ static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
 	struct shader_test_bo *src = &(test_priv.src);
 	struct shader_test_bo *dst = &(test_priv.dst);
 	struct shader_test_bo *cmd = &(test_priv.cmd);
-	amdgpu_bo_handle resources[5];
+	struct shader_test_bo *vtx_attributes_mem = &(test_priv.vtx_attributes_mem);
+	amdgpu_bo_handle resources[6];
 	uint8_t *ptr_dst;
 	uint8_t *ptr_src;
 	uint32_t *ptr_cmd;
@@ -1551,6 +1959,14 @@ static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
 	r = shader_test_bo_alloc(test_info->device_handle, dst);
 	CU_ASSERT_EQUAL(r, 0);
 
+	if (test_info->version == AMDGPU_TEST_GFX_V11) {
+		vtx_attributes_mem->size = 0x4040000;
+		vtx_attributes_mem->heap = AMDGPU_GEM_DOMAIN_VRAM;
+
+		r = shader_test_bo_alloc(test_info->device_handle, vtx_attributes_mem);
+		CU_ASSERT_EQUAL(r, 0);
+	}
+
 	amdgpu_draw_init(&test_priv);
 
 	amdgpu_draw_setup_and_write_drawblt_surf_info(&test_priv);
@@ -1584,6 +2000,16 @@ static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
 		ptr_cmd[i++] = test_info->hang_slow ? 0 : 0x400;
 		i++;
 		break;
+	case AMDGPU_TEST_GFX_V11:
+		ptr_cmd[i++] = 0xc;
+		ptr_cmd[i++] = src->mc_address >> 8;
+		ptr_cmd[i++] = src->mc_address >> 40 | 0xc4b00000;
+		ptr_cmd[i++] = test_info->hang_slow ? 0x1ffc1ff : 0x7c007;
+		ptr_cmd[i++] = test_info->hang_slow ? 0x90a00fac : 0x90600fac;
+		i += 2;
+		ptr_cmd[i++] = 0x400;
+		i++;
+		break;
 	}
 
 	ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 4);
@@ -1609,6 +2035,8 @@ static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
 	resources[i++] = ps_bo->bo;
 	resources[i++] = vs_bo->bo;
 	resources[i++] = cmd->bo;
+	if (vtx_attributes_mem->size)
+		resources[i++] = vtx_attributes_mem->bo;
 	r = amdgpu_bo_list_create(test_info->device_handle, i, resources, NULL, &bo_list);
 	CU_ASSERT_EQUAL(r, 0);
 
@@ -1654,6 +2082,11 @@ static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info)
 	r = amdgpu_bo_list_destroy(bo_list);
 	CU_ASSERT_EQUAL(r, 0);
 
+	if (vtx_attributes_mem->size) {
+		r = shader_test_bo_free(vtx_attributes_mem);
+		CU_ASSERT_EQUAL(r, 0);
+	}
+
 	r = shader_test_bo_free(src);
 	CU_ASSERT_EQUAL(r, 0);