Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, and new

packet type for making it possible to address whole tcl vector space
    and have a larger count)

shared-core/radeon_drm.h

@@ -161,7 +161,8 @@
 #define R200_EMIT_PP_TXCTLALL_3                     91
 #define R200_EMIT_PP_TXCTLALL_4                     92
 #define R200_EMIT_PP_TXCTLALL_5                     93
-#define RADEON_MAX_STATE_PACKETS                    94
+#define R200_EMIT_VAP_PVS_CNTL                      94
+#define RADEON_MAX_STATE_PACKETS                    95
 
 /* Commands understood by cmd_buffer ioctl.  More can be added but
  * obviously these can't be removed or changed:
@@ -176,6 +177,7 @@
 #define RADEON_CMD_WAIT         8	/* emit hw wait commands -- note:
 					 *  doesn't make the cpu wait, just
 					 *  the graphics hardware */
+#define RADEON_CMD_VECLINEAR	9       /* another r200 stopgap */
 
 typedef union {
 	int i;
@@ -191,6 +193,9 @@ typedef union {
 	struct {
 		unsigned char cmd_type, offset, stride, count;
 	} vectors;
+	struct {
+		unsigned char cmd_type, addr_lo, addr_hi, count;
+	} veclinear;
 	struct {
 		unsigned char cmd_type, buf_idx, pad0, pad1;
 	} dma;

shared-core/radeon_drv.h

@@ -38,7 +38,7 @@
 
 #define DRIVER_NAME		"radeon"
 #define DRIVER_DESC		"ATI Radeon"
-#define DRIVER_DATE		"20060519"
+#define DRIVER_DATE		"20060524"
 
 /* Interface history:
  *
@@ -93,10 +93,12 @@
  * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
  * 1.23- Add new radeon memory map work from benh
  * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
+ * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
+ *       new packet type)
  */
 
 #define DRIVER_MAJOR		1
-#define DRIVER_MINOR		24
+#define DRIVER_MINOR		25
 #define DRIVER_PATCHLEVEL	0
 
 /*
@@ -905,6 +907,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
 #define R200_PP_AFS_0                     0x2f80
 #define R200_PP_AFS_1                     0x2f00 /* same as txcblend_0 */
 
+#define R200_VAP_PVS_CNTL_1               0x22D0
+
 /* MPEG settings from VHA code */
 #define RADEON_VHA_SETTO16_1                       0x2694
 #define RADEON_VHA_SETTO16_2                       0x2680

shared-core/radeon_state.c

@@ -249,6 +249,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
 	case R200_EMIT_PP_TXCTLALL_3:
 	case R200_EMIT_PP_TXCTLALL_4:
 	case R200_EMIT_PP_TXCTLALL_5:
+	case R200_EMIT_VAP_PVS_CNTL:
 		/* These packets don't contain memory offsets */
 		break;
 
@@ -626,6 +627,7 @@ static struct {
 	{R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
 	{R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
 	{R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
+	{R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
 };
 
 /* ================================================================
@@ -2643,6 +2645,32 @@ static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
 	return 0;
 }
 
+static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
+					  drm_radeon_cmd_header_t header,
+					  drm_radeon_kcmd_buffer_t *cmdbuf)
+{
+	int sz = header.veclinear.count * 4;
+	int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
+	RING_LOCALS;
+
+        if (!sz)
+                return 0;
+        if (sz * 4 > cmdbuf->bufsz)
+                return DRM_ERR(EINVAL);
+
+	BEGIN_RING(5 + sz);
+	OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
+	OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
+	OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
+	OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
+	OUT_RING_TABLE(cmdbuf->buf, sz);
+	ADVANCE_RING();
+
+	cmdbuf->buf += sz * sizeof(int);
+	cmdbuf->bufsz -= sz * sizeof(int);
+	return 0;
+}
+
 static int radeon_emit_packet3(drm_device_t * dev,
 			       drm_file_t * filp_priv,
 			       drm_radeon_kcmd_buffer_t *cmdbuf)
@@ -2906,6 +2934,14 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS)
 				goto err;
 			}
 			break;
+		case RADEON_CMD_VECLINEAR:
+			DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
+			if (radeon_emit_veclinear(dev_priv, header, &cmdbuf)) {
+				DRM_ERROR("radeon_emit_veclinear failed\n");
+				goto err;
+			}
+			break;
+
 		default:
 			DRM_ERROR("bad cmd_type %d at %p\n",
 				  header.header.cmd_type,