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headers: Sync up kernel changes to use kernel types instead of stdint.h. 

This pulls in pieces of drm-next d65d31388a23 ("Merge tag
'drm-misc-next-fixes-2017-11-07' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next")

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
main
Eric Anholt 2017-11-08 11:22:55 -08:00
parent 59808bcacd
commit f696698e02
4 changed files with 144 additions and 149 deletions
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9
include/drm/README
View File

@ -102,19 +102,14 @@ Status: Trivial.
nouveau_drm.h nouveau_drm.h
- Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs, - Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs,
enums, using stdint.h over the __u* types. enums
Status: ? Status: ?
qxl_drm.h
- Using the stdint.h uint*_t over the respective __u* ones
Status: Trivial.
r128_drm.h r128_drm.h
- Broken compat ioctls. - Broken compat ioctls.
radeon_drm.h radeon_drm.h
- Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls, - Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls
using stdint types.
- Both kernel and libdrm: missing padding - - Both kernel and libdrm: missing padding -
drm_radeon_gem_{create,{g,s}et_tiling,set_domain} others ? drm_radeon_gem_{create,{g,s}et_tiling,set_domain} others ?
Status: ? Status: ?

84
include/drm/nouveau_drm.h
View File

@ -111,34 +111,34 @@ struct drm_nouveau_setparam {
#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
struct drm_nouveau_gem_info { struct drm_nouveau_gem_info {
uint32_t handle; __u32 handle;
uint32_t domain; __u32 domain;
uint64_t size; __u64 size;
uint64_t offset; __u64 offset;
uint64_t map_handle; __u64 map_handle;
uint32_t tile_mode; __u32 tile_mode;
uint32_t tile_flags; __u32 tile_flags;
}; };
struct drm_nouveau_gem_new { struct drm_nouveau_gem_new {
struct drm_nouveau_gem_info info; struct drm_nouveau_gem_info info;
uint32_t channel_hint; __u32 channel_hint;
uint32_t align; __u32 align;
}; };
#define NOUVEAU_GEM_MAX_BUFFERS 1024 #define NOUVEAU_GEM_MAX_BUFFERS 1024
struct drm_nouveau_gem_pushbuf_bo_presumed { struct drm_nouveau_gem_pushbuf_bo_presumed {
uint32_t valid; __u32 valid;
uint32_t domain; __u32 domain;
uint64_t offset; __u64 offset;
}; };
struct drm_nouveau_gem_pushbuf_bo { struct drm_nouveau_gem_pushbuf_bo {
uint64_t user_priv; __u64 user_priv;
uint32_t handle; __u32 handle;
uint32_t read_domains; __u32 read_domains;
uint32_t write_domains; __u32 write_domains;
uint32_t valid_domains; __u32 valid_domains;
struct drm_nouveau_gem_pushbuf_bo_presumed presumed; struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
}; };
@ -147,47 +147,47 @@ struct drm_nouveau_gem_pushbuf_bo {
#define NOUVEAU_GEM_RELOC_OR (1 << 2) #define NOUVEAU_GEM_RELOC_OR (1 << 2)
#define NOUVEAU_GEM_MAX_RELOCS 1024 #define NOUVEAU_GEM_MAX_RELOCS 1024
struct drm_nouveau_gem_pushbuf_reloc { struct drm_nouveau_gem_pushbuf_reloc {
uint32_t reloc_bo_index; __u32 reloc_bo_index;
uint32_t reloc_bo_offset; __u32 reloc_bo_offset;
uint32_t bo_index; __u32 bo_index;
uint32_t flags; __u32 flags;
uint32_t data; __u32 data;
uint32_t vor; __u32 vor;
uint32_t tor; __u32 tor;
}; };
#define NOUVEAU_GEM_MAX_PUSH 512 #define NOUVEAU_GEM_MAX_PUSH 512
struct drm_nouveau_gem_pushbuf_push { struct drm_nouveau_gem_pushbuf_push {
uint32_t bo_index; __u32 bo_index;
uint32_t pad; __u32 pad;
uint64_t offset; __u64 offset;
uint64_t length; __u64 length;
}; };
struct drm_nouveau_gem_pushbuf { struct drm_nouveau_gem_pushbuf {
uint32_t channel; __u32 channel;
uint32_t nr_buffers; __u32 nr_buffers;
uint64_t buffers; __u64 buffers;
uint32_t nr_relocs; __u32 nr_relocs;
uint32_t nr_push; __u32 nr_push;
uint64_t relocs; __u64 relocs;
uint64_t push; __u64 push;
uint32_t suffix0; __u32 suffix0;
uint32_t suffix1; __u32 suffix1;
uint64_t vram_available; __u64 vram_available;
uint64_t gart_available; __u64 gart_available;
}; };
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
struct drm_nouveau_gem_cpu_prep { struct drm_nouveau_gem_cpu_prep {
uint32_t handle; __u32 handle;
uint32_t flags; __u32 flags;
}; };
struct drm_nouveau_gem_cpu_fini { struct drm_nouveau_gem_cpu_fini {
uint32_t handle; __u32 handle;
}; };
enum nouveau_bus_type { enum nouveau_bus_type {

72
include/drm/qxl_drm.h
View File

@ -52,14 +52,14 @@ extern "C" {
#define DRM_QXL_ALLOC_SURF 0x06 #define DRM_QXL_ALLOC_SURF 0x06
struct drm_qxl_alloc { struct drm_qxl_alloc {
uint32_t size; __u32 size;
uint32_t handle; /* 0 is an invalid handle */ __u32 handle; /* 0 is an invalid handle */
}; };
struct drm_qxl_map { struct drm_qxl_map {
uint64_t offset; /* use for mmap system call */ __u64 offset; /* use for mmap system call */
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
}; };
/* /*
@ -72,59 +72,59 @@ struct drm_qxl_map {
#define QXL_RELOC_TYPE_SURF 2 #define QXL_RELOC_TYPE_SURF 2
struct drm_qxl_reloc { struct drm_qxl_reloc {
uint64_t src_offset; /* offset into src_handle or src buffer */ __u64 src_offset; /* offset into src_handle or src buffer */
uint64_t dst_offset; /* offset in dest handle */ __u64 dst_offset; /* offset in dest handle */
uint32_t src_handle; /* dest handle to compute address from */ __u32 src_handle; /* dest handle to compute address from */
uint32_t dst_handle; /* 0 if to command buffer */ __u32 dst_handle; /* 0 if to command buffer */
uint32_t reloc_type; __u32 reloc_type;
uint32_t pad; __u32 pad;
}; };
struct drm_qxl_command { struct drm_qxl_command {
uint64_t command; /* void* */ __u64 command; /* void* */
uint64_t relocs; /* struct drm_qxl_reloc* */ __u64 relocs; /* struct drm_qxl_reloc* */
uint32_t type; __u32 type;
uint32_t command_size; __u32 command_size;
uint32_t relocs_num; __u32 relocs_num;
uint32_t pad; __u32 pad;
}; };
/* XXX: call it drm_qxl_commands? */ /* XXX: call it drm_qxl_commands? */
struct drm_qxl_execbuffer { struct drm_qxl_execbuffer {
uint32_t flags; /* for future use */ __u32 flags; /* for future use */
uint32_t commands_num; __u32 commands_num;
uint64_t commands; /* struct drm_qxl_command* */ __u64 commands; /* struct drm_qxl_command* */
}; };
struct drm_qxl_update_area { struct drm_qxl_update_area {
uint32_t handle; __u32 handle;
uint32_t top; __u32 top;
uint32_t left; __u32 left;
uint32_t bottom; __u32 bottom;
uint32_t right; __u32 right;
uint32_t pad; __u32 pad;
}; };
#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */ #define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
#define QXL_PARAM_MAX_RELOCS 2 #define QXL_PARAM_MAX_RELOCS 2
struct drm_qxl_getparam { struct drm_qxl_getparam {
uint64_t param; __u64 param;
uint64_t value; __u64 value;
}; };
/* these are one bit values */ /* these are one bit values */
struct drm_qxl_clientcap { struct drm_qxl_clientcap {
uint32_t index; __u32 index;
uint32_t pad; __u32 pad;
}; };
struct drm_qxl_alloc_surf { struct drm_qxl_alloc_surf {
uint32_t format; __u32 format;
uint32_t width; __u32 width;
uint32_t height; __u32 height;
int32_t stride; __s32 stride;
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
}; };
#define DRM_IOCTL_QXL_ALLOC \ #define DRM_IOCTL_QXL_ALLOC \

128
include/drm/radeon_drm.h
View File

@ -797,9 +797,9 @@ typedef struct drm_radeon_surface_free {
#define RADEON_GEM_DOMAIN_VRAM 0x4 #define RADEON_GEM_DOMAIN_VRAM 0x4
struct drm_radeon_gem_info { struct drm_radeon_gem_info {
uint64_t gart_size; __u64 gart_size;
uint64_t vram_size; __u64 vram_size;
uint64_t vram_visible; __u64 vram_visible;
}; };
#define RADEON_GEM_NO_BACKING_STORE (1 << 0) #define RADEON_GEM_NO_BACKING_STORE (1 << 0)
@ -811,11 +811,11 @@ struct drm_radeon_gem_info {
#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
struct drm_radeon_gem_create { struct drm_radeon_gem_create {
uint64_t size; __u64 size;
uint64_t alignment; __u64 alignment;
uint32_t handle; __u32 handle;
uint32_t initial_domain; __u32 initial_domain;
uint32_t flags; __u32 flags;
}; };
/* /*
@ -829,10 +829,10 @@ struct drm_radeon_gem_create {
#define RADEON_GEM_USERPTR_REGISTER (1 << 3) #define RADEON_GEM_USERPTR_REGISTER (1 << 3)
struct drm_radeon_gem_userptr { struct drm_radeon_gem_userptr {
uint64_t addr; __u64 addr;
uint64_t size; __u64 size;
uint32_t flags; __u32 flags;
uint32_t handle; __u32 handle;
}; };
#define RADEON_TILING_MACRO 0x1 #define RADEON_TILING_MACRO 0x1
@ -855,72 +855,72 @@ struct drm_radeon_gem_userptr {
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
struct drm_radeon_gem_set_tiling { struct drm_radeon_gem_set_tiling {
uint32_t handle; __u32 handle;
uint32_t tiling_flags; __u32 tiling_flags;
uint32_t pitch; __u32 pitch;
}; };
struct drm_radeon_gem_get_tiling { struct drm_radeon_gem_get_tiling {
uint32_t handle; __u32 handle;
uint32_t tiling_flags; __u32 tiling_flags;
uint32_t pitch; __u32 pitch;
}; };
struct drm_radeon_gem_mmap { struct drm_radeon_gem_mmap {
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
uint64_t offset; __u64 offset;
uint64_t size; __u64 size;
uint64_t addr_ptr; __u64 addr_ptr;
}; };
struct drm_radeon_gem_set_domain { struct drm_radeon_gem_set_domain {
uint32_t handle; __u32 handle;
uint32_t read_domains; __u32 read_domains;
uint32_t write_domain; __u32 write_domain;
}; };
struct drm_radeon_gem_wait_idle { struct drm_radeon_gem_wait_idle {
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
}; };
struct drm_radeon_gem_busy { struct drm_radeon_gem_busy {
uint32_t handle; __u32 handle;
uint32_t domain; __u32 domain;
}; };
struct drm_radeon_gem_pread { struct drm_radeon_gem_pread {
/** Handle for the object being read. */ /** Handle for the object being read. */
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
/** Offset into the object to read from */ /** Offset into the object to read from */
uint64_t offset; __u64 offset;
/** Length of data to read */ /** Length of data to read */
uint64_t size; __u64 size;
/** Pointer to write the data into. */ /** Pointer to write the data into. */
/* void *, but pointers are not 32/64 compatible */ /* void *, but pointers are not 32/64 compatible */
uint64_t data_ptr; __u64 data_ptr;
}; };
struct drm_radeon_gem_pwrite { struct drm_radeon_gem_pwrite {
/** Handle for the object being written to. */ /** Handle for the object being written to. */
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
/** Offset into the object to write to */ /** Offset into the object to write to */
uint64_t offset; __u64 offset;
/** Length of data to write */ /** Length of data to write */
uint64_t size; __u64 size;
/** Pointer to read the data from. */ /** Pointer to read the data from. */
/* void *, but pointers are not 32/64 compatible */ /* void *, but pointers are not 32/64 compatible */
uint64_t data_ptr; __u64 data_ptr;
}; };
/* Sets or returns a value associated with a buffer. */ /* Sets or returns a value associated with a buffer. */
struct drm_radeon_gem_op { struct drm_radeon_gem_op {
uint32_t handle; /* buffer */ __u32 handle; /* buffer */
uint32_t op; /* RADEON_GEM_OP_* */ __u32 op; /* RADEON_GEM_OP_* */
uint64_t value; /* input or return value */ __u64 value; /* input or return value */
}; };
#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
@ -940,11 +940,11 @@ struct drm_radeon_gem_op {
#define RADEON_VM_PAGE_SNOOPED (1 << 4) #define RADEON_VM_PAGE_SNOOPED (1 << 4)
struct drm_radeon_gem_va { struct drm_radeon_gem_va {
uint32_t handle; __u32 handle;
uint32_t operation; __u32 operation;
uint32_t vm_id; __u32 vm_id;
uint32_t flags; __u32 flags;
uint64_t offset; __u64 offset;
}; };
#define RADEON_CHUNK_ID_RELOCS 0x01 #define RADEON_CHUNK_ID_RELOCS 0x01
@ -966,29 +966,29 @@ struct drm_radeon_gem_va {
/* 0 = normal, + = higher priority, - = lower priority */ /* 0 = normal, + = higher priority, - = lower priority */
struct drm_radeon_cs_chunk { struct drm_radeon_cs_chunk {
uint32_t chunk_id; __u32 chunk_id;
uint32_t length_dw; __u32 length_dw;
uint64_t chunk_data; __u64 chunk_data;
}; };
/* drm_radeon_cs_reloc.flags */ /* drm_radeon_cs_reloc.flags */
#define RADEON_RELOC_PRIO_MASK (0xf << 0) #define RADEON_RELOC_PRIO_MASK (0xf << 0)
struct drm_radeon_cs_reloc { struct drm_radeon_cs_reloc {
uint32_t handle; __u32 handle;
uint32_t read_domains; __u32 read_domains;
uint32_t write_domain; __u32 write_domain;
uint32_t flags; __u32 flags;
}; };
struct drm_radeon_cs { struct drm_radeon_cs {
uint32_t num_chunks; __u32 num_chunks;
uint32_t cs_id; __u32 cs_id;
/* this points to uint64_t * which point to cs chunks */ /* this points to __u64 * which point to cs chunks */
uint64_t chunks; __u64 chunks;
/* updates to the limits after this CS ioctl */ /* updates to the limits after this CS ioctl */
uint64_t gart_limit; __u64 gart_limit;
uint64_t vram_limit; __u64 vram_limit;
}; };
#define RADEON_INFO_DEVICE_ID 0x00 #define RADEON_INFO_DEVICE_ID 0x00
@ -1047,9 +1047,9 @@ struct drm_radeon_cs {
#define RADEON_INFO_GPU_RESET_COUNTER 0x26 #define RADEON_INFO_GPU_RESET_COUNTER 0x26
struct drm_radeon_info { struct drm_radeon_info {
uint32_t request; __u32 request;
uint32_t pad; __u32 pad;
uint64_t value; __u64 value;
}; };
/* Those correspond to the tile index to use, this is to explicitly state /* Those correspond to the tile index to use, this is to explicitly state