headers: Sync up kernel changes to use kernel types instead of stdint.h.
This pulls in pieces of drm-next d65d31388a23 ("Merge tag
'drm-misc-next-fixes-2017-11-07' of
git://anongit.freedesktop.org/drm/drm-misc into drm-next")
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
main
Eric Anholt
parent
59808bcacd
commit
f696698e02
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@ -102,19 +102,14 @@ Status: Trivial.
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nouveau_drm.h
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- Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs,
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enums, using stdint.h over the __u* types.
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enums
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Status: ?
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qxl_drm.h
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- Using the stdint.h uint*_t over the respective __u* ones
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Status: Trivial.
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r128_drm.h
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- Broken compat ioctls.
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radeon_drm.h
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- Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls,
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using stdint types.
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- Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls
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- Both kernel and libdrm: missing padding -
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drm_radeon_gem_{create,{g,s}et_tiling,set_domain} others ?
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Status: ?
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@ -111,34 +111,34 @@ struct drm_nouveau_setparam {
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#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
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struct drm_nouveau_gem_info {
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uint32_t handle;
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uint32_t domain;
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uint64_t size;
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uint64_t offset;
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uint64_t map_handle;
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uint32_t tile_mode;
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uint32_t tile_flags;
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__u32 handle;
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__u32 domain;
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__u64 size;
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__u64 offset;
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__u64 map_handle;
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__u32 tile_mode;
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__u32 tile_flags;
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};
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struct drm_nouveau_gem_new {
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struct drm_nouveau_gem_info info;
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uint32_t channel_hint;
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uint32_t align;
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__u32 channel_hint;
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__u32 align;
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};
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#define NOUVEAU_GEM_MAX_BUFFERS 1024
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struct drm_nouveau_gem_pushbuf_bo_presumed {
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uint32_t valid;
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uint32_t domain;
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uint64_t offset;
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__u32 valid;
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__u32 domain;
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__u64 offset;
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};
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struct drm_nouveau_gem_pushbuf_bo {
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uint64_t user_priv;
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uint32_t handle;
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uint32_t read_domains;
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uint32_t write_domains;
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uint32_t valid_domains;
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__u64 user_priv;
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__u32 handle;
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__u32 read_domains;
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__u32 write_domains;
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__u32 valid_domains;
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struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
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};
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@ -147,47 +147,47 @@ struct drm_nouveau_gem_pushbuf_bo {
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#define NOUVEAU_GEM_RELOC_OR (1 << 2)
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#define NOUVEAU_GEM_MAX_RELOCS 1024
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struct drm_nouveau_gem_pushbuf_reloc {
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uint32_t reloc_bo_index;
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uint32_t reloc_bo_offset;
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uint32_t bo_index;
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uint32_t flags;
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uint32_t data;
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uint32_t vor;
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uint32_t tor;
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__u32 reloc_bo_index;
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__u32 reloc_bo_offset;
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__u32 bo_index;
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__u32 flags;
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__u32 data;
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__u32 vor;
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__u32 tor;
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};
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#define NOUVEAU_GEM_MAX_PUSH 512
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struct drm_nouveau_gem_pushbuf_push {
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uint32_t bo_index;
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uint32_t pad;
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uint64_t offset;
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uint64_t length;
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__u32 bo_index;
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__u32 pad;
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__u64 offset;
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__u64 length;
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};
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struct drm_nouveau_gem_pushbuf {
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uint32_t channel;
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uint32_t nr_buffers;
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uint64_t buffers;
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uint32_t nr_relocs;
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uint32_t nr_push;
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uint64_t relocs;
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uint64_t push;
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uint32_t suffix0;
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uint32_t suffix1;
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uint64_t vram_available;
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uint64_t gart_available;
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__u32 channel;
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__u32 nr_buffers;
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__u64 buffers;
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__u32 nr_relocs;
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__u32 nr_push;
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__u64 relocs;
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__u64 push;
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__u32 suffix0;
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__u32 suffix1;
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__u64 vram_available;
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__u64 gart_available;
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};
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#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
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#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
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#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
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struct drm_nouveau_gem_cpu_prep {
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uint32_t handle;
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uint32_t flags;
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__u32 handle;
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__u32 flags;
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};
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struct drm_nouveau_gem_cpu_fini {
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uint32_t handle;
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__u32 handle;
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};
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enum nouveau_bus_type {
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@ -52,14 +52,14 @@ extern "C" {
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#define DRM_QXL_ALLOC_SURF 0x06
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struct drm_qxl_alloc {
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uint32_t size;
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uint32_t handle; /* 0 is an invalid handle */
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__u32 size;
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__u32 handle; /* 0 is an invalid handle */
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};
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struct drm_qxl_map {
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uint64_t offset; /* use for mmap system call */
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uint32_t handle;
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uint32_t pad;
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__u64 offset; /* use for mmap system call */
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__u32 handle;
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__u32 pad;
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};
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/*
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@ -72,59 +72,59 @@ struct drm_qxl_map {
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#define QXL_RELOC_TYPE_SURF 2
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struct drm_qxl_reloc {
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uint64_t src_offset; /* offset into src_handle or src buffer */
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uint64_t dst_offset; /* offset in dest handle */
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uint32_t src_handle; /* dest handle to compute address from */
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uint32_t dst_handle; /* 0 if to command buffer */
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uint32_t reloc_type;
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uint32_t pad;
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__u64 src_offset; /* offset into src_handle or src buffer */
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__u64 dst_offset; /* offset in dest handle */
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__u32 src_handle; /* dest handle to compute address from */
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__u32 dst_handle; /* 0 if to command buffer */
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__u32 reloc_type;
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__u32 pad;
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};
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struct drm_qxl_command {
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uint64_t command; /* void* */
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uint64_t relocs; /* struct drm_qxl_reloc* */
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uint32_t type;
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uint32_t command_size;
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uint32_t relocs_num;
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uint32_t pad;
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__u64 command; /* void* */
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__u64 relocs; /* struct drm_qxl_reloc* */
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__u32 type;
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__u32 command_size;
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__u32 relocs_num;
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__u32 pad;
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};
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/* XXX: call it drm_qxl_commands? */
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struct drm_qxl_execbuffer {
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uint32_t flags; /* for future use */
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uint32_t commands_num;
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uint64_t commands; /* struct drm_qxl_command* */
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__u32 flags; /* for future use */
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__u32 commands_num;
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__u64 commands; /* struct drm_qxl_command* */
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};
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struct drm_qxl_update_area {
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uint32_t handle;
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uint32_t top;
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uint32_t left;
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uint32_t bottom;
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uint32_t right;
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uint32_t pad;
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__u32 handle;
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__u32 top;
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__u32 left;
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__u32 bottom;
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__u32 right;
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__u32 pad;
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};
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#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
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#define QXL_PARAM_MAX_RELOCS 2
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struct drm_qxl_getparam {
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uint64_t param;
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uint64_t value;
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__u64 param;
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__u64 value;
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};
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/* these are one bit values */
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struct drm_qxl_clientcap {
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uint32_t index;
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uint32_t pad;
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__u32 index;
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__u32 pad;
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};
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struct drm_qxl_alloc_surf {
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uint32_t format;
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uint32_t width;
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uint32_t height;
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int32_t stride;
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uint32_t handle;
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uint32_t pad;
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__u32 format;
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__u32 width;
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__u32 height;
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__s32 stride;
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__u32 handle;
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__u32 pad;
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};
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#define DRM_IOCTL_QXL_ALLOC \
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@ -797,9 +797,9 @@ typedef struct drm_radeon_surface_free {
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#define RADEON_GEM_DOMAIN_VRAM 0x4
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struct drm_radeon_gem_info {
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uint64_t gart_size;
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uint64_t vram_size;
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uint64_t vram_visible;
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__u64 gart_size;
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__u64 vram_size;
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__u64 vram_visible;
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};
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#define RADEON_GEM_NO_BACKING_STORE (1 << 0)
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@ -811,11 +811,11 @@ struct drm_radeon_gem_info {
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#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
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struct drm_radeon_gem_create {
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uint64_t size;
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uint64_t alignment;
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uint32_t handle;
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uint32_t initial_domain;
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uint32_t flags;
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__u64 size;
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__u64 alignment;
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__u32 handle;
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__u32 initial_domain;
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__u32 flags;
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};
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/*
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@ -829,10 +829,10 @@ struct drm_radeon_gem_create {
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#define RADEON_GEM_USERPTR_REGISTER (1 << 3)
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struct drm_radeon_gem_userptr {
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uint64_t addr;
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uint64_t size;
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uint32_t flags;
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uint32_t handle;
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__u64 addr;
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__u64 size;
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__u32 flags;
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__u32 handle;
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};
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#define RADEON_TILING_MACRO 0x1
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@ -855,72 +855,72 @@ struct drm_radeon_gem_userptr {
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#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
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struct drm_radeon_gem_set_tiling {
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uint32_t handle;
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uint32_t tiling_flags;
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uint32_t pitch;
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__u32 handle;
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__u32 tiling_flags;
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__u32 pitch;
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};
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struct drm_radeon_gem_get_tiling {
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uint32_t handle;
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uint32_t tiling_flags;
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uint32_t pitch;
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__u32 handle;
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__u32 tiling_flags;
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__u32 pitch;
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};
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struct drm_radeon_gem_mmap {
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uint32_t handle;
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uint32_t pad;
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uint64_t offset;
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uint64_t size;
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uint64_t addr_ptr;
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__u32 handle;
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__u32 pad;
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__u64 offset;
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__u64 size;
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__u64 addr_ptr;
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};
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struct drm_radeon_gem_set_domain {
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uint32_t handle;
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uint32_t read_domains;
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uint32_t write_domain;
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__u32 handle;
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__u32 read_domains;
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__u32 write_domain;
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};
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struct drm_radeon_gem_wait_idle {
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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};
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struct drm_radeon_gem_busy {
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uint32_t handle;
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uint32_t domain;
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__u32 handle;
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__u32 domain;
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};
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struct drm_radeon_gem_pread {
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/** Handle for the object being read. */
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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/** Offset into the object to read from */
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uint64_t offset;
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__u64 offset;
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/** Length of data to read */
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uint64_t size;
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__u64 size;
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/** Pointer to write the data into. */
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/* void *, but pointers are not 32/64 compatible */
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uint64_t data_ptr;
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__u64 data_ptr;
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};
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struct drm_radeon_gem_pwrite {
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/** Handle for the object being written to. */
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uint32_t handle;
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uint32_t pad;
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__u32 handle;
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__u32 pad;
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/** Offset into the object to write to */
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uint64_t offset;
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__u64 offset;
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/** Length of data to write */
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uint64_t size;
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__u64 size;
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/** Pointer to read the data from. */
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/* void *, but pointers are not 32/64 compatible */
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uint64_t data_ptr;
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__u64 data_ptr;
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};
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/* Sets or returns a value associated with a buffer. */
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struct drm_radeon_gem_op {
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uint32_t handle; /* buffer */
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uint32_t op; /* RADEON_GEM_OP_* */
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uint64_t value; /* input or return value */
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__u32 handle; /* buffer */
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__u32 op; /* RADEON_GEM_OP_* */
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__u64 value; /* input or return value */
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};
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#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
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@ -940,11 +940,11 @@ struct drm_radeon_gem_op {
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#define RADEON_VM_PAGE_SNOOPED (1 << 4)
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struct drm_radeon_gem_va {
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uint32_t handle;
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uint32_t operation;
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uint32_t vm_id;
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uint32_t flags;
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uint64_t offset;
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__u32 handle;
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__u32 operation;
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__u32 vm_id;
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__u32 flags;
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__u64 offset;
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};
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#define RADEON_CHUNK_ID_RELOCS 0x01
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@ -966,29 +966,29 @@ struct drm_radeon_gem_va {
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/* 0 = normal, + = higher priority, - = lower priority */
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struct drm_radeon_cs_chunk {
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uint32_t chunk_id;
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uint32_t length_dw;
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uint64_t chunk_data;
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__u32 chunk_id;
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__u32 length_dw;
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__u64 chunk_data;
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};
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/* drm_radeon_cs_reloc.flags */
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#define RADEON_RELOC_PRIO_MASK (0xf << 0)
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struct drm_radeon_cs_reloc {
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uint32_t handle;
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uint32_t read_domains;
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uint32_t write_domain;
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uint32_t flags;
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__u32 handle;
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__u32 read_domains;
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__u32 write_domain;
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__u32 flags;
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};
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struct drm_radeon_cs {
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uint32_t num_chunks;
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uint32_t cs_id;
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/* this points to uint64_t * which point to cs chunks */
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uint64_t chunks;
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__u32 num_chunks;
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__u32 cs_id;
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/* this points to __u64 * which point to cs chunks */
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__u64 chunks;
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/* updates to the limits after this CS ioctl */
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uint64_t gart_limit;
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uint64_t vram_limit;
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__u64 gart_limit;
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__u64 vram_limit;
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};
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#define RADEON_INFO_DEVICE_ID 0x00
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@ -1047,9 +1047,9 @@ struct drm_radeon_cs {
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#define RADEON_INFO_GPU_RESET_COUNTER 0x26
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struct drm_radeon_info {
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uint32_t request;
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uint32_t pad;
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uint64_t value;
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__u32 request;
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__u32 pad;
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__u64 value;
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};
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/* Those correspond to the tile index to use, this is to explicitly state
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