Setup MTRRs for frame buffer and aperture manually on Savage3D and
Savage4-based cards. Automatic setup in drm_initmap doesn't work due to the weird alignment and size of the aperture.main
parent
6c8a3194f4
commit
ffc51f1f32
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@ -76,6 +76,7 @@ static struct drm_driver driver = {
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.dev_priv_size = sizeof(drm_savage_buf_priv_t),
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.preinit = savage_preinit,
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.postinit = postinit,
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.postcleanup = savage_postcleanup,
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.reclaim_buffers = savage_reclaim_buffers,
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.get_map_ofs = drm_core_get_map_ofs,
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.get_reg_ofs = drm_core_get_reg_ofs,
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@ -283,10 +283,19 @@ void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf)
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entry->next = next;
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}
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/*
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* Initalize permanent mappings. On Savage4 and SavageIX the alignment
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* and size of the aperture is not suitable for automatic MTRR setup
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* in drm_initmap. Therefore we do it manually before the maps are
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* initialized. We also need to take care of deleting the MTRRs in
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* postcleanup.
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*
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* FIXME: this is linux-specific
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*/
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int savage_preinit(drm_device_t *dev, unsigned long chipset)
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{
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drm_savage_private_t *dev_priv;
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unsigned int mmio_base, fb_base, fb_size, aperture_base;
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unsigned long mmio_base, fb_base, fb_size, aperture_base;
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int ret = 0;
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dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
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@ -297,21 +306,61 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
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dev->dev_private = (void *)dev_priv;
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dev_priv->chipset = (enum savage_family)chipset;
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dev_priv->mtrr[0].handle = -1;
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dev_priv->mtrr[1].handle = -1;
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dev_priv->mtrr[2].handle = -1;
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if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
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fb_base = pci_resource_start(dev->pdev, 0);
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fb_size = SAVAGE_FB_SIZE_S3;
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mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
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aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
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/* this should always be true */
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if (pci_resource_len(dev->pdev, 0) == 0x08000000) {
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/* Don't make MMIO write-cobining! We need 3
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* MTRRs. */
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dev_priv->mtrr[0].base = fb_base;
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dev_priv->mtrr[0].size = 0x01000000;
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dev_priv->mtrr[0].handle = mtrr_add(
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dev_priv->mtrr[0].base, dev_priv->mtrr[0].size,
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MTRR_TYPE_WRCOMB, 1);
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dev_priv->mtrr[1].base = fb_base+0x02000000;
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dev_priv->mtrr[1].size = 0x02000000;
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dev_priv->mtrr[1].handle = mtrr_add(
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dev_priv->mtrr[1].base, dev_priv->mtrr[1].size,
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MTRR_TYPE_WRCOMB, 1);
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dev_priv->mtrr[2].base = fb_base+0x04000000;
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dev_priv->mtrr[2].size = 0x04000000;
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dev_priv->mtrr[2].handle = mtrr_add(
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dev_priv->mtrr[2].base, dev_priv->mtrr[2].size,
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MTRR_TYPE_WRCOMB, 1);
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} else {
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DRM_ERROR("strange pci_resource_len %08lx\n",
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pci_resource_len(dev->pdev, 0));
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}
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} else if (chipset != S3_SUPERSAVAGE && chipset != S3_SAVAGE2000) {
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mmio_base = pci_resource_start(dev->pdev, 0);
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fb_base = pci_resource_start(dev->pdev, 1);
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fb_size = SAVAGE_FB_SIZE_S4;
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aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
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/* this should always be true */
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if (pci_resource_len(dev->pdev, 1) == 0x08000000) {
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/* Can use one MTRR to cover both fb and
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* aperture. */
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dev_priv->mtrr[0].base = fb_base;
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dev_priv->mtrr[0].size = 0x08000000;
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dev_priv->mtrr[0].handle = mtrr_add(
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dev_priv->mtrr[0].base, dev_priv->mtrr[0].size,
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MTRR_TYPE_WRCOMB, 1);
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} else {
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DRM_ERROR("strange pci_resource_len %08lx\n",
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pci_resource_len(dev->pdev, 1));
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}
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} else {
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mmio_base = pci_resource_start(dev->pdev, 0);
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fb_base = pci_resource_start(dev->pdev, 1);
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fb_size = pci_resource_len(dev->pdev, 1);
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aperture_base = pci_resource_start(dev->pdev, 2);
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/* Automatic MTRR setup will do the right thing. */
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}
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if ((ret = drm_initmap(dev, mmio_base, SAVAGE_MMIO_SIZE,
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@ -335,6 +384,25 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset)
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return ret;
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}
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/*
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* Delete MTRRs and free device-private data.
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*/
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int savage_postcleanup(drm_device_t *dev)
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{
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drm_savage_private_t *dev_priv = dev->dev_private;
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int i;
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for (i = 0; i < 3; ++i)
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if (dev_priv->mtrr[i].handle >= 0)
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mtrr_del(dev_priv->mtrr[i].handle,
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dev_priv->mtrr[i].base,
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dev_priv->mtrr[i].size);
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drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
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return 0;
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}
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static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init)
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{
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drm_savage_private_t *dev_priv = dev->dev_private;
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@ -140,6 +140,11 @@ typedef struct drm_savage_private {
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drm_local_map_t *agp_textures;
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drm_local_map_t *cmd_dma;
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struct {
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int handle;
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unsigned long base, size;
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} mtrr[3];
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/* BCI and status-related stuff */
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volatile uint32_t *status_ptr, *bci_ptr;
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uint32_t status_used_mask;
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@ -177,6 +182,7 @@ extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
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unsigned int flags);
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extern void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf);
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extern int savage_preinit(drm_device_t *dev, unsigned long chipset);
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extern int savage_postcleanup(drm_device_t *dev);
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extern int savage_do_cleanup_bci(drm_device_t *dev);
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extern void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp);
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