Commit Graph

58 Commits (main)

Author SHA1 Message Date
Jerome Glisse 325e2e52a9 radeon: always properly initialize stencil_offset field
Reported-by: Vadim Girlin <vadimgirlin@gmail.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11 15:01:12 -04:00
Alex Deucher c2b77a02d4 radeon: fall back to 1D tiling only with broken kernels
Certain cards report the the wrong bank setup which causes
surface init to fail in the ddx and leads to no accel.
If we hit an invalid tiling parameter, just set a default
value and disable 2D tiling.

Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=43448

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-07 10:43:18 -04:00
Michel Dänzer 481234f290 radeon: Add Southern Islands PCI IDs.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-05-16 18:49:44 +02:00
Alex Deucher c50cc24690 radeon: add TN surface support
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-03-20 19:33:09 -04:00
Jerome Glisse 9b3ad51ae5 radeon: fix pitch alignment for scanout buffer
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-13 20:46:43 -05:00
Jerome Glisse 10c0837780 radeon: fix surface API for good before anyone start relying on it
The mipmap level computation was wrong, we need to know the block
width, height, depth of compressed texture to properly compute this.
Change API to provide block width, height, depth instead of nblk_x,
nblk_y, nblk_z.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-03 14:42:47 -05:00
Jerome Glisse 6a720cb866 radeon: surface fix macro -> micro tile fallback
We need to force 1D tiling only on old kernel the fallback was
broken along the way.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-02 18:36:42 -05:00
Jerome Glisse c51f7f0e46 radeon: add surface allocator helper v10
The surface allocator is able to build complete miptree when allocating
surface for r600/r700/evergreen/northern islands GPU family. It also
compute bo size and alignment for render buffer, depth buffer and
scanout buffer.

v2 fix r6xx/r7xx 2D tiling width align computation
v3 add tile split support and fix 1d texture alignment
v4 rework to more properly support compressed format, split surface pixel
   size and surface element size in separate fields
v5 support texture array (still issue on r6xx)
v6 split surface value computation and mipmap tree building, rework eg
   and newer computation
v7 add a check for tile split and 2d tiled
v8 initialize mode value before testing it in all case, reenable
   2D macro tile mode on r6xx for cubemap and array. Fix cubemap
   to force array size to the number of face.
v9 fix handling of stencil buffer on evergreen
v10 on evergreen depth buffer need to have enough room for a stencil
    buffer just after depth one

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01 17:11:29 -05:00