Commit Graph

60 Commits (0452be882607f2d1601f4e592a11ccf543f5f9ca)

Author SHA1 Message Date
Ben Skeggs 0ef097b598 nv50: use same dma object for fb/tt access
We depend on the VM fully now for memory protection, separate DMA objects
for VRAM and GART are unneccesary.  However, until the next interface break
(soon) a client can't depend on the objects being the same and must still
call NV_OBJ_SET_DMA_* methods appropriately.
2008-07-18 18:25:33 +02:00
Ben Skeggs 4872ac9c62 nouveau: interface changes for nv5x 3d 2008-07-18 17:44:51 +02:00
Maarten Maathuis 062d850620 nv50: s/FALSE/false && s/TRUE/true 2008-07-03 09:08:01 +02:00
Maarten Maathuis 91c742663a NV50: use list_head item instead of list_head head to avoid confusion 2008-06-27 18:58:13 +02:00
Maarten Maathuis 4d85d5d251 NV50: i misunderstood NOUVEAU_MEM_INTERNAL, so remove it 2008-06-25 15:27:07 +02:00
Maarten Maathuis 09b67dda0b NV50: Some cleanup and fixes. 2008-06-25 15:16:38 +02:00
Ben Skeggs 5a0164d1e1 nouveau: allocate drm-use vram buffers from end of vram.
This avoids seeing garbage from engine setup etc before X gets around
to pointing the CRTCs at a new scanout buffer.  Not actually a noticable
problem before G80 as PRAMIN is forced to the end of VRAM by the hardware
already.
2008-06-25 09:55:14 +02:00
Maarten Maathuis 473a1997ac NV50: Initial import of kernel modesetting. 2008-06-22 16:29:00 +02:00
Ben Skeggs 1766e1c07b nv50: force channel vram access through vm
If we ever want to be able to use the 3D engine we have no choice.  It
appears that the tiling setup (required for 3D on G8x) is in the page tables.

The immediate benefit of this change however is that it's now not possible
for a client to use the GPU to render over the top of important engine setup
tables, which also live in VRAM.

G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping
of real vram pages to their offset within the start of a channel's VRAM
DMA object and only populate a single PDE for VRAM use.
2008-03-13 00:23:52 +11:00
Stuart Bennett f13936f7fc nouveau: move AGP reset to mem_init_agp
Also, power cycle PGRAPH when resetting AGP -- it seems to fix problems encountered by p0g on nv25
2008-03-11 16:45:35 +00:00
Dave Airlie d5c0101252 ttm: make sure userspace can't destroy kernel create memory managers
this adds something to say the kernel initialised the memory region not
the userspace. and blocks userspace from deallocating kernel areas
2008-03-06 05:37:54 +10:00
Stephane Marchesin cd87e6352b nouveau: no GART on ia64 either. 2008-02-16 03:50:29 +01:00
Maarten Maathuis 7c726086dd nouveau: Fix warning in nouveau_mem.c 2008-01-23 16:40:19 +01:00
Stephane Marchesin 269d518008 nouveau: make mem alloc debug a little more verbose. 2008-01-14 03:16:42 +01:00
Dave Airlie 7f6bf84c23 drm: remove lots of spurious whitespace.
Kernel "cleanfile" script run.
2007-11-05 12:42:22 +10:00
Ben Skeggs 9a999e57af nouveau: crappy ttm mm init, disabled for now. 2007-11-05 01:20:32 +11:00
Stephane Marchesin 5766d81074 nouveau: don't use AGP on PPC. It's a hopeless case. 2007-11-01 15:49:10 +01:00
Stephane Marchesin 9a115080e8 nouveau: fix IGP 2007-10-23 02:19:17 +02:00
Ben Skeggs 9fdab5b5c5 nouveau: revert unintended change. 2007-10-16 14:43:57 +11:00
Ben Skeggs 6398325ba1 nouveau: Handle multiple PFIFO exceptions per irq, cleanup output. 2007-10-16 13:27:27 +11:00
Jeremy Kolb 811e43f9e2 nouveau: fix warning. 2007-10-14 10:56:17 -04:00
Stephane Marchesin 69b11f44f0 nouveau: give nv03 the last cut. 2007-08-31 01:40:00 +02:00
Stephane Marchesin 76337bdb19 nouveau: fix the comment and debug message for PCIGART size 2007-08-22 04:20:50 +02:00
Patrice Mandin c8760c7999 Check also for Linux, as it's not supported on different OS 2007-08-19 18:45:01 +02:00
Patrice Mandin a122e7dabf Function pci_get_bus_and_slot needs 2.6.19 or later 2007-08-19 18:41:18 +02:00
Ben Skeggs 8a4d7f34d9 nouveau: Detect memory on NFORCE/NFORCE2 correctly. 2007-08-17 01:12:46 +10:00
Ben Skeggs a615d2fde7 nouveau: Turn some messages into DRM_DEBUGs.. 2007-08-15 14:01:35 +10:00
Stephane Marchesin ac24f328ec nouveau: Bump PCI GART to 16MB 2007-08-06 17:16:05 +02:00
Ben Skeggs 97770db720 nouveau: Various internal and external API changes
1. DRM_NOUVEAU_GPUOBJ_FREE
	Used to free GPU objects.  The obvious usage case is for Gr objects,
	but notifiers can also be destroyed in the same way.

	GPU objects gain a destructor method and private data fields with
	this change, so other specialised cases (like notifiers) can be
	implemented on top of gpuobjs.

2. DRM_NOUVEAU_CHANNEL_FREE

3. DRM_NOUVEAU_CARD_INIT
	Ideally we'd do init during module load, but this isn't currently
	possible.  Doing init during firstopen() is bad as X has a love of
	opening/closing the DRM many times during startup.  Once the
	modesetting-101 branch is merged this can go away.

	IRQs are enabled in nouveau_card_init() now, rather than having the
	X server call drmCtlInstHandler().  We'll need this for when we give
	the kernel module its own channel.

4. DRM_NOUVEAU_GETPARAM
	Add CHIPSET_ID value, which will return the chipset id derived
	from NV_PMC_BOOT_0.

4. Use list_* in a few places, rather than home-brewed stuff.
2007-08-06 21:45:18 +10:00
Eric Anholt 5b38e13416 Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.
The data is now in kernel space, copied in/out as appropriate according to the
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures.  This also means that XFree86 4.2.0 support for i810 DRM
is lost.
2007-07-20 18:16:42 -07:00
Eric Anholt c1119b1b09 Replace filp in ioctl arguments with drm_file *file_priv.
As a fallout, replace filp storage with file_priv storage for "unique
identifier of a client" all over the DRM.  There is a 1:1 mapping, so this
should be a noop.  This could be a minor performance improvement, as everything
on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls
went the other direction.
2007-07-20 13:39:45 -07:00
Eric Anholt e39286eb5e Remove DRM_ERR OS macro.
This was used to make all ioctl handlers return -errno on linux and errno on
*BSD.  Instead, just return -errno in shared code, and flip sign on return from
shared code to *BSD code.
2007-07-20 12:53:52 -07:00
Ben Skeggs ec67c2def9 nouveau: G8x PCIEGART
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it.
2007-07-17 13:51:14 +10:00
Dave Airlie 21ee6fbfb8 drm: remove drmP.h internal typedefs 2007-07-16 12:32:51 +10:00
Dave Airlie b95ac8b7b3 drm: detypedef drm.h and fixup all problems 2007-07-16 11:22:15 +10:00
Patrice Mandin bc7d6c76fa nouveau: nv10 and nv11/15 are different 2007-07-14 18:32:11 +02:00
Ben Skeggs 0029713451 nouveau: nuke internal typedefs, and drm_device_t use. 2007-07-13 15:09:31 +10:00
Ben Skeggs 851c950d98 nouveau: unbreak AGP 2007-07-13 02:18:59 +10:00
Ben Skeggs 522a0c868c nouveau: nuke left over debug message 2007-07-12 11:39:45 +10:00
Ben Skeggs 750371cb6e nouveau: separate region_offset into map_handle and offset. 2007-07-12 10:46:57 +10:00
Arthur Huillet 5fbdf9da8b fixed object creation code to not Oops on 64bits, worked around memalloc not working on 64bit for PCIGART 2007-07-12 02:35:39 +02:00
Arthur Huillet b301a9051b NV50 will not attempt to use PCIGART now 2007-07-11 15:01:37 +02:00
Arthur Huillet d26ae22c2b fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will probably still have a problem 2007-07-11 14:56:27 +02:00
Arthur Huillet 694e1c5c3f Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. 2007-07-11 02:35:10 +02:00
Ben Skeggs c806bba466 nouveau/nv50: Initial channel/object support
Should be OK on G84 for a single channel, multiple channels *almost* work.

Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs 163f852612 nouveau: rewrite gpu object code
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.

Handle per-channel private instmem areas.  This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?

Everything that touches PRAMIN is a GPU object.
2007-07-09 16:16:44 +10:00
Ben Skeggs 68ecf61647 nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit 2007-06-28 03:26:44 +10:00
Ben Skeggs 18a6d1c9c3 nouveau: simplify PRAMIN access 2007-06-28 03:26:44 +10:00
Ben Skeggs 695599f18d nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
For various reasons, this ioctl was a bad idea.

At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.

However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers).  Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
Matthieu Castet 59784116bf nouveau : fix fifo context size for nv10 2007-05-08 21:20:25 +02:00